arm64: add ESR_ELx EC.SVE
Add the SVE exception class, so that SVE exceptions are not printed
as 'unknown' exceptions.
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
diff --git a/lib/arm64/asm/esr.h b/lib/arm64/asm/esr.h
index 8c35163..335343c 100644
--- a/lib/arm64/asm/esr.h
+++ b/lib/arm64/asm/esr.h
@@ -26,6 +26,7 @@
#define ESR_EL1_EC_SVC32 (0x11)
#define ESR_EL1_EC_SVC64 (0x15)
#define ESR_EL1_EC_SYS64 (0x18)
+#define ESR_EL1_EC_SVE (0x19)
#define ESR_EL1_EC_IABT_EL0 (0x20)
#define ESR_EL1_EC_IABT_EL1 (0x21)
#define ESR_EL1_EC_PC_ALIGN (0x22)
diff --git a/lib/arm64/processor.c b/lib/arm64/processor.c
index 06fd7cf..eb93fd7 100644
--- a/lib/arm64/processor.c
+++ b/lib/arm64/processor.c
@@ -43,6 +43,7 @@
[ESR_EL1_EC_SVC32] = "SVC32",
[ESR_EL1_EC_SVC64] = "SVC64",
[ESR_EL1_EC_SYS64] = "SYS64",
+ [ESR_EL1_EC_SVE] = "SVE",
[ESR_EL1_EC_IABT_EL0] = "IABT_EL0",
[ESR_EL1_EC_IABT_EL1] = "IABT_EL1",
[ESR_EL1_EC_PC_ALIGN] = "PC_ALIGN",
