Merge branch 'riscv/sbi' into 'master'
riscv: Add TIME SBI extension tests
See merge request kvm-unit-tests/kvm-unit-tests!62
diff --git a/lib/riscv/asm/csr.h b/lib/riscv/asm/csr.h
index 5260851..24b333e 100644
--- a/lib/riscv/asm/csr.h
+++ b/lib/riscv/asm/csr.h
@@ -4,12 +4,19 @@
#include <linux/const.h>
#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
#define CSR_STVEC 0x105
#define CSR_SSCRATCH 0x140
#define CSR_SEPC 0x141
#define CSR_SCAUSE 0x142
#define CSR_STVAL 0x143
+#define CSR_SIP 0x144
+#define CSR_STIMECMP 0x14d
+#define CSR_STIMECMPH 0x15d
#define CSR_SATP 0x180
+#define CSR_TIME 0xc01
+
+#define SR_SIE _AC(0x00000002, UL)
/* Exception cause high bit - is an interrupt if set */
#define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
@@ -34,6 +41,20 @@
#define EXC_VIRTUAL_INST_FAULT 22
#define EXC_STORE_GUEST_PAGE_FAULT 23
+/* Interrupt causes */
+#define IRQ_S_SOFT 1
+#define IRQ_VS_SOFT 2
+#define IRQ_S_TIMER 5
+#define IRQ_VS_TIMER 6
+#define IRQ_S_EXT 9
+#define IRQ_VS_EXT 10
+#define IRQ_S_GEXT 12
+#define IRQ_PMU_OVF 13
+
+#define IE_TIE (_AC(0x1, UL) << IRQ_S_TIMER)
+
+#define IP_TIP IE_TIE
+
#ifndef __ASSEMBLY__
#define csr_swap(csr, val) \
diff --git a/lib/riscv/asm/delay.h b/lib/riscv/asm/delay.h
new file mode 100644
index 0000000..31379ea
--- /dev/null
+++ b/lib/riscv/asm/delay.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef _ASMRISCV_DELAY_H_
+#define _ASMRISCV_DELAY_H_
+
+#include <libcflat.h>
+#include <asm/setup.h>
+
+extern void delay(uint64_t cycles);
+extern void udelay(unsigned long usecs);
+
+static inline uint64_t usec_to_cycles(uint64_t usec)
+{
+ return (timebase_frequency * usec) / 1000000;
+}
+
+#endif /* _ASMRISCV_DELAY_H_ */
diff --git a/lib/riscv/asm/processor.h b/lib/riscv/asm/processor.h
index 32c499d..4c9ad96 100644
--- a/lib/riscv/asm/processor.h
+++ b/lib/riscv/asm/processor.h
@@ -4,7 +4,8 @@
#include <asm/csr.h>
#include <asm/ptrace.h>
-#define EXCEPTION_CAUSE_MAX 16
+#define EXCEPTION_CAUSE_MAX 24
+#define INTERRUPT_CAUSE_MAX 16
typedef void (*exception_fn)(struct pt_regs *);
@@ -13,6 +14,7 @@
unsigned long hartid;
unsigned long isa[1];
exception_fn exception_handlers[EXCEPTION_CAUSE_MAX];
+ exception_fn interrupt_handlers[INTERRUPT_CAUSE_MAX];
};
static inline struct thread_info *current_thread_info(void)
@@ -20,7 +22,18 @@
return (struct thread_info *)csr_read(CSR_SSCRATCH);
}
+static inline void local_irq_enable(void)
+{
+ csr_set(CSR_SSTATUS, SR_SIE);
+}
+
+static inline void local_irq_disable(void)
+{
+ csr_clear(CSR_SSTATUS, SR_SIE);
+}
+
void install_exception_handler(unsigned long cause, void (*handler)(struct pt_regs *));
+void install_irq_handler(unsigned long cause, void (*handler)(struct pt_regs *));
void do_handle_exception(struct pt_regs *regs);
void thread_info_init(void);
diff --git a/lib/riscv/asm/sbi.h b/lib/riscv/asm/sbi.h
index d82a384..73ab543 100644
--- a/lib/riscv/asm/sbi.h
+++ b/lib/riscv/asm/sbi.h
@@ -16,6 +16,7 @@
enum sbi_ext_id {
SBI_EXT_BASE = 0x10,
+ SBI_EXT_TIME = 0x54494d45,
SBI_EXT_HSM = 0x48534d,
SBI_EXT_SRST = 0x53525354,
};
@@ -37,6 +38,10 @@
SBI_EXT_HSM_HART_SUSPEND,
};
+enum sbi_ext_time_fid {
+ SBI_EXT_TIME_SET_TIMER = 0,
+};
+
struct sbiret {
long error;
long value;
@@ -49,6 +54,7 @@
void sbi_shutdown(void);
struct sbiret sbi_hart_start(unsigned long hartid, unsigned long entry, unsigned long sp);
+long sbi_probe(int ext);
#endif /* !__ASSEMBLY__ */
#endif /* _ASMRISCV_SBI_H_ */
diff --git a/lib/riscv/asm/setup.h b/lib/riscv/asm/setup.h
index 7f81a70..a13159b 100644
--- a/lib/riscv/asm/setup.h
+++ b/lib/riscv/asm/setup.h
@@ -7,6 +7,7 @@
#define NR_CPUS 16
extern struct thread_info cpus[NR_CPUS];
extern int nr_cpus;
+extern uint64_t timebase_frequency;
int hartid_to_cpu(unsigned long hartid);
void io_init(void);
diff --git a/lib/riscv/asm/timer.h b/lib/riscv/asm/timer.h
new file mode 100644
index 0000000..b3514d3
--- /dev/null
+++ b/lib/riscv/asm/timer.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef _ASMRISCV_TIMER_H_
+#define _ASMRISCV_TIMER_H_
+
+#include <asm/csr.h>
+
+extern void timer_get_frequency(void);
+
+static inline uint64_t timer_get_cycles(void)
+{
+ return csr_read(CSR_TIME);
+}
+
+static inline void timer_irq_enable(void)
+{
+ csr_set(CSR_SIE, IE_TIE);
+}
+
+static inline void timer_irq_disable(void)
+{
+ csr_clear(CSR_SIE, IE_TIE);
+}
+
+#endif /* _ASMRISCV_TIMER_H_ */
diff --git a/lib/riscv/delay.c b/lib/riscv/delay.c
new file mode 100644
index 0000000..d4f76c2
--- /dev/null
+++ b/lib/riscv/delay.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2024, James Raphael Tiovalen <jamestiotio@gmail.com>
+ */
+#include <libcflat.h>
+#include <asm/barrier.h>
+#include <asm/delay.h>
+#include <asm/timer.h>
+
+void delay(uint64_t cycles)
+{
+ uint64_t start = timer_get_cycles();
+
+ while ((timer_get_cycles() - start) < cycles)
+ cpu_relax();
+}
+
+void udelay(unsigned long usecs)
+{
+ delay(usec_to_cycles((uint64_t)usecs));
+}
diff --git a/lib/riscv/processor.c b/lib/riscv/processor.c
index ece7cbf..0dffadc 100644
--- a/lib/riscv/processor.c
+++ b/lib/riscv/processor.c
@@ -36,10 +36,21 @@
{
struct thread_info *info = current_thread_info();
- assert(regs->cause < EXCEPTION_CAUSE_MAX);
- if (info->exception_handlers[regs->cause]) {
- info->exception_handlers[regs->cause](regs);
- return;
+ if (regs->cause & CAUSE_IRQ_FLAG) {
+ unsigned long irq_cause = regs->cause & ~CAUSE_IRQ_FLAG;
+
+ assert(irq_cause < INTERRUPT_CAUSE_MAX);
+ if (info->interrupt_handlers[irq_cause]) {
+ info->interrupt_handlers[irq_cause](regs);
+ return;
+ }
+ } else {
+ assert(regs->cause < EXCEPTION_CAUSE_MAX);
+
+ if (info->exception_handlers[regs->cause]) {
+ info->exception_handlers[regs->cause](regs);
+ return;
+ }
}
show_regs(regs);
@@ -47,6 +58,14 @@
abort();
}
+void install_irq_handler(unsigned long cause, void (*handler)(struct pt_regs *))
+{
+ struct thread_info *info = current_thread_info();
+
+ assert(cause < INTERRUPT_CAUSE_MAX);
+ info->interrupt_handlers[cause] = handler;
+}
+
void install_exception_handler(unsigned long cause, void (*handler)(struct pt_regs *))
{
struct thread_info *info = current_thread_info();
diff --git a/lib/riscv/sbi.c b/lib/riscv/sbi.c
index f39134c..3d4236e 100644
--- a/lib/riscv/sbi.c
+++ b/lib/riscv/sbi.c
@@ -38,3 +38,16 @@
{
return sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_START, hartid, entry, sp, 0, 0, 0);
}
+
+long sbi_probe(int ext)
+{
+ struct sbiret ret;
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_GET_SPEC_VERSION, 0, 0, 0, 0, 0, 0);
+ assert(!ret.error && ret.value >= 2);
+
+ ret = sbi_ecall(SBI_EXT_BASE, SBI_EXT_BASE_PROBE_EXT, ext, 0, 0, 0, 0, 0);
+ assert(!ret.error);
+
+ return ret.value;
+}
diff --git a/lib/riscv/setup.c b/lib/riscv/setup.c
index 50ffb0d..e0b5f6f 100644
--- a/lib/riscv/setup.c
+++ b/lib/riscv/setup.c
@@ -20,6 +20,7 @@
#include <asm/page.h>
#include <asm/processor.h>
#include <asm/setup.h>
+#include <asm/timer.h>
#define VA_BASE ((phys_addr_t)3 * SZ_1G)
#if __riscv_xlen == 64
@@ -38,6 +39,7 @@
struct thread_info cpus[NR_CPUS];
int nr_cpus;
+uint64_t timebase_frequency;
static struct mem_region riscv_mem_regions[NR_MEM_REGIONS + 1];
@@ -199,6 +201,7 @@
mem_init(PAGE_ALIGN(__pa(freemem)));
cpu_init();
+ timer_get_frequency();
thread_info_init();
io_init();
@@ -264,6 +267,7 @@
}
cpu_init();
+ timer_get_frequency();
thread_info_init();
io_init();
initrd_setup();
diff --git a/lib/riscv/timer.c b/lib/riscv/timer.c
new file mode 100644
index 0000000..d78d254
--- /dev/null
+++ b/lib/riscv/timer.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2024, James Raphael Tiovalen <jamestiotio@gmail.com>
+ */
+#include <libcflat.h>
+#include <devicetree.h>
+#include <asm/setup.h>
+#include <asm/timer.h>
+
+void timer_get_frequency(void)
+{
+ const struct fdt_property *prop;
+ u32 *data;
+ int cpus, len;
+
+ assert_msg(dt_available(), "ACPI not yet supported");
+
+ const void *fdt = dt_fdt();
+
+ cpus = fdt_path_offset(fdt, "/cpus");
+ assert(cpus >= 0);
+
+ prop = fdt_get_property(fdt, cpus, "timebase-frequency", &len);
+ assert(prop != NULL && len == 4);
+
+ data = (u32 *)prop->data;
+ timebase_frequency = fdt32_to_cpu(*data);
+}
diff --git a/riscv/Makefile b/riscv/Makefile
index 919a3eb..b0cd613 100644
--- a/riscv/Makefile
+++ b/riscv/Makefile
@@ -30,6 +30,7 @@
cflatobjs += lib/on-cpus.o
cflatobjs += lib/vmalloc.o
cflatobjs += lib/riscv/bitops.o
+cflatobjs += lib/riscv/delay.o
cflatobjs += lib/riscv/io.o
cflatobjs += lib/riscv/isa.o
cflatobjs += lib/riscv/mmu.o
@@ -38,6 +39,7 @@
cflatobjs += lib/riscv/setup.o
cflatobjs += lib/riscv/smp.o
cflatobjs += lib/riscv/stack.o
+cflatobjs += lib/riscv/timer.o
ifeq ($(ARCH),riscv32)
cflatobjs += lib/ldiv32.o
endif
diff --git a/riscv/sbi.c b/riscv/sbi.c
index 762e971..2438c49 100644
--- a/riscv/sbi.c
+++ b/riscv/sbi.c
@@ -6,7 +6,15 @@
*/
#include <libcflat.h>
#include <stdlib.h>
+#include <limits.h>
+#include <asm/barrier.h>
+#include <asm/csr.h>
+#include <asm/delay.h>
+#include <asm/isa.h>
+#include <asm/processor.h>
#include <asm/sbi.h>
+#include <asm/smp.h>
+#include <asm/timer.h>
static void help(void)
{
@@ -19,6 +27,11 @@
return sbi_ecall(SBI_EXT_BASE, fid, arg0, 0, 0, 0, 0, 0);
}
+static struct sbiret __time_sbi_ecall(unsigned long stime_value)
+{
+ return sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0, 0, 0, 0, 0);
+}
+
static bool env_or_skip(const char *env)
{
if (!getenv(env)) {
@@ -83,6 +96,10 @@
expected = getenv("PROBE_EXT") ? strtol(getenv("PROBE_EXT"), NULL, 0) : 1;
ret = __base_sbi_ecall(SBI_EXT_BASE_PROBE_EXT, SBI_EXT_BASE);
gen_report(&ret, 0, expected);
+ report_prefix_push("unavailable");
+ ret = __base_sbi_ecall(SBI_EXT_BASE_PROBE_EXT, 0xb000000);
+ gen_report(&ret, 0, 0);
+ report_prefix_pop();
report_prefix_pop();
report_prefix_push("mvendorid");
@@ -112,6 +129,125 @@
report_prefix_pop();
}
+struct timer_info {
+ bool timer_works;
+ bool mask_timer_irq;
+ bool timer_irq_set;
+ bool timer_irq_cleared;
+ unsigned long timer_irq_count;
+};
+
+static struct timer_info timer_info;
+
+static bool timer_irq_pending(void)
+{
+ return csr_read(CSR_SIP) & IP_TIP;
+}
+
+static void timer_irq_handler(struct pt_regs *regs)
+{
+ timer_info.timer_works = true;
+
+ if (timer_info.timer_irq_count < ULONG_MAX)
+ ++timer_info.timer_irq_count;
+
+ if (timer_irq_pending())
+ timer_info.timer_irq_set = true;
+
+ if (timer_info.mask_timer_irq)
+ timer_irq_disable();
+ else
+ __time_sbi_ecall(ULONG_MAX);
+
+ if (!timer_irq_pending())
+ timer_info.timer_irq_cleared = true;
+}
+
+static void timer_check_set_timer(bool mask_timer_irq)
+{
+ struct sbiret ret;
+ unsigned long begin, end, duration;
+ const char *mask_test_str = mask_timer_irq ? " for mask irq test" : "";
+ unsigned long d = getenv("TIMER_DELAY") ? strtol(getenv("TIMER_DELAY"), NULL, 0) : 200000;
+ unsigned long margin = getenv("TIMER_MARGIN") ? strtol(getenv("TIMER_MARGIN"), NULL, 0) : 200000;
+
+ d = usec_to_cycles(d);
+ margin = usec_to_cycles(margin);
+
+ timer_info = (struct timer_info){ .mask_timer_irq = mask_timer_irq };
+ begin = timer_get_cycles();
+ ret = __time_sbi_ecall(begin + d);
+
+ report(!ret.error, "set timer%s", mask_test_str);
+ if (ret.error)
+ report_info("set timer%s failed with %ld\n", mask_test_str, ret.error);
+
+ while ((end = timer_get_cycles()) <= (begin + d + margin) && !timer_info.timer_works)
+ cpu_relax();
+
+ report(timer_info.timer_works, "timer interrupt received%s", mask_test_str);
+ report(timer_info.timer_irq_set, "pending timer interrupt bit set in irq handler%s", mask_test_str);
+
+ if (!mask_timer_irq) {
+ report(timer_info.timer_irq_set && timer_info.timer_irq_cleared,
+ "pending timer interrupt bit cleared by setting timer to -1");
+ }
+
+ if (timer_info.timer_works) {
+ duration = end - begin;
+ report(duration >= d && duration <= (d + margin), "timer delay honored%s", mask_test_str);
+ }
+
+ report(timer_info.timer_irq_count == 1, "timer interrupt received exactly once%s", mask_test_str);
+}
+
+static void check_time(void)
+{
+ bool pending;
+
+ report_prefix_push("time");
+
+ if (!sbi_probe(SBI_EXT_TIME)) {
+ report_skip("time extension not available");
+ report_prefix_pop();
+ return;
+ }
+
+ report_prefix_push("set_timer");
+
+ install_irq_handler(IRQ_S_TIMER, timer_irq_handler);
+ local_irq_enable();
+ if (cpu_has_extension(smp_processor_id(), ISA_SSTC)) {
+ csr_write(CSR_STIMECMP, ULONG_MAX);
+ if (__riscv_xlen == 32)
+ csr_write(CSR_STIMECMPH, ULONG_MAX);
+ }
+ timer_irq_enable();
+
+ timer_check_set_timer(false);
+
+ if (csr_read(CSR_SIE) & IE_TIE)
+ timer_check_set_timer(true);
+ else
+ report_skip("timer irq enable bit is not writable, skipping mask irq test");
+
+ timer_irq_disable();
+ __time_sbi_ecall(0);
+ pending = timer_irq_pending();
+ report(pending, "timer immediately pending by setting timer to 0");
+ __time_sbi_ecall(ULONG_MAX);
+ if (pending)
+ report(!timer_irq_pending(), "pending timer cleared while masked");
+ else
+ report_skip("timer is not pending, skipping timer cleared while masked test");
+
+ local_irq_disable();
+ install_irq_handler(IRQ_S_TIMER, NULL);
+
+ report_prefix_pop();
+ report_prefix_pop();
+}
+
int main(int argc, char **argv)
{
@@ -122,6 +258,7 @@
report_prefix_push("sbi");
check_base();
+ check_time();
return report_summary();
}
diff --git a/riscv/unittests.cfg b/riscv/unittests.cfg
index 50c67e3..cbd36bf 100644
--- a/riscv/unittests.cfg
+++ b/riscv/unittests.cfg
@@ -9,7 +9,7 @@
[selftest]
file = selftest.flat
-smp = 16
+smp = $MAX_SMP
extra_params = -append 'foo bar baz'
groups = selftest