commit c595c36114e1b1e23a63651b08aa2a12f1b8bcd2
author Mingwei Zhang <mizhang@google.com> Wed Sep 27 22:54:41 2023 +0000
committer Sean Christopherson <seanjc@google.com> Wed Jun 05 13:41:29 2024 -0700
tree c390464f9c2eebd73473aff0331898c600c01792
parent 8d0f574f4e4d14ecaeec625090da3afcd63bf56c

x86/pmu: Clear mask in PMI handler to allow delivering subsequent PMIs

Clear mask in PMI handler to allow subsequent PMI delivered. SDM 11.5.1
Local Vector Table mentions: "When the local APIC handles a
performance-monitoring counters interrupt, it automatically sets the mask
flag in the LVT performance counter register. This flag is set to 1 on
reset.  It can be cleared only by software."

Previously KVM vPMU does not set the mask when injecting the PMI, so there
is no issue for this test to work correctly. To ensure the test still works
after the KVM fix merges, add the mask clearing behavior to PMI handler.

Signed-off-by: Mingwei Zhang <mizhang@google.com>
Link: https://lore.kernel.org/r/20230927225441.871050-1-mizhang@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>

x86/pmu.c

diff --git a/x86/pmu.c b/x86/pmu.c
index 7062c1a..ce9abbe 100644
--- a/x86/pmu.c
+++ b/x86/pmu.c
@@ -69,6 +69,7 @@
 static void cnt_overflow(isr_regs_t *regs)
 {
 	irq_received++;
+	apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
 	apic_write(APIC_EOI, 0);
 }
 

x86/pmu_pebs.c

diff --git a/x86/pmu_pebs.c b/x86/pmu_pebs.c
index df8e736..77875c4 100644
--- a/x86/pmu_pebs.c
+++ b/x86/pmu_pebs.c
@@ -110,6 +110,7 @@
 
 static void cnt_overflow(isr_regs_t *regs)
 {
+	apic_write(APIC_LVTPC, apic_read(APIC_LVTPC) & ~APIC_LVT_MASKED);
 	apic_write(APIC_EOI, 0);
 }