)]}' { "log": [ { "commit": "5a221342a025948fa7d84f0c404748f6ba57f3ad", "tree": "f93716837a306b129328fd5d6c9164dc3b0b370f", "parents": [ "277b89313f8afad437d75d278ce01d8166a2f702" ], "author": { "name": "Ryosuke Yasuoka", "email": "ryasuoka@redhat.com", "time": "Thu Aug 20 08:49:03 2026 +0000" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Tue Sep 08 15:33:43 2026 +0200" }, "message": "svm: Add SMI handler for svm_intr_intercept_mix_smi test\n\nL1 intercepts L2\u0027s SMI and the SMI is still pending at L0. When L1\nre-enables GIF via stgi(), L0 delivers the SMI to L1.\n\nIf SMBASE has not been relocated and no SMI handler has been installed,\nL1 enters SMM and executes garbage at the default entry point, causing\nan abort.\n\nInstall a trivial SMI handler at the default SMBASE entry point so L1\ncan return from SMM.\n\nSigned-off-by: Ryosuke Yasuoka \u003cryasuoka@redhat.com\u003e\nReviewed-by: Maxim Levitsky \u003cmlevitsk@redhat.com\u003e\nMessage-ID: \u003c20260820-add_smi_handler-v2-1-80d7316d5dde@redhat.com\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "277b89313f8afad437d75d278ce01d8166a2f702", "tree": "65486636c55e8c959c7624d234b7b5b8e36e817a", "parents": [ "714bfd622b00cb5e8f2dad9e620641a0adb74ab7" ], "author": { "name": "Xudong Hao", "email": "xudong.hao@intel.com", "time": "Tue Jul 07 07:02:40 2026 +0000" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Tue Sep 08 15:23:39 2026 +0200" }, "message": "x86/vmx: Skip LAM CR3 bits in 32-bit guest reserved bit tests\n\nAccording to Intel SDM 4.4.1 \"Linear-Address Masking\" (LAM), CR3 bits\n61 (LAM_U57) and 62 (LAM_U48) are LAM control bits, not reserved. Skip\nthe LAM control bits in the CR3 reserved-bit loops when LAM is\nsupported for vmx_pae_test and vmx_pse_test.\n\nFixes: 55b77db1 (\"vmx: add a test for 32-bit guest PAE paging PDPTEs\")\nFixes: feef9d92 (\"vmx: add test for 32-bit non-PAE guest\")\n\nSigned-off-by: Xudong Hao \u003cxudong.hao@intel.com\u003e\nMessage-ID: \u003c20260707070240.78295-1-xudong.hao@intel.com\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "714bfd622b00cb5e8f2dad9e620641a0adb74ab7", "tree": "6759564c4b2e9a2dcd38d0293805a702e64e08a7", "parents": [ "42e3bf31317d31b81bbf519bf87c6e30905743eb", "865a34f0de2eb13c548ca089e4b8aa9988c25158" ], "author": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon Sep 07 17:10:34 2026 +0200" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon Sep 07 17:10:34 2026 +0200" }, "message": "Merge branch \u0027fix-export\u0027 into \u0027master\u0027\n\nscripts/mkstandalone: avoid running `export` when config.mak lacks a variable\n\nSee merge request kvm-unit-tests/kvm-unit-tests!89" }, { "commit": "42e3bf31317d31b81bbf519bf87c6e30905743eb", "tree": "cee185da0ee0d09eecfcb496721d02701d9843e1", "parents": [ "f20b0b8d3373ab489ef3ed9f2ebdf6839bcddd9c", "8bf102b93eecf879a2313cc30beef88e00f140d7" ], "author": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon Sep 07 16:59:22 2026 +0200" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon Sep 07 16:59:22 2026 +0200" }, "message": "Merge branch \u0027s390x-pull-2026-08\u0027 into \u0027master\u0027\n\ns390x: stflei test, fixes and sie lib rework\n\nSee merge request kvm-unit-tests/kvm-unit-tests!88" }, { "commit": "865a34f0de2eb13c548ca089e4b8aa9988c25158", "tree": "9082c0e5134ac67d8c811adb579175e121b0ccd6", "parents": [ "f20b0b8d3373ab489ef3ed9f2ebdf6839bcddd9c" ], "author": { "name": "Po-Hsu Lin", "email": "po-hsu.lin@canonical.com", "time": "Mon Aug 31 12:37:29 2026 +0800" }, "committer": { "name": "Po-Hsu Lin", "email": "po-hsu.lin@canonical.com", "time": "Mon Aug 31 12:37:33 2026 +0800" }, "message": "scripts/mkstandalone: avoid running `export` when config.mak lacks a variable\n\nconfig_export() emits `export` into the generated standalone test script.\nTARGET\u003d is only written to config.mak for arm/arm64/riscv32/riscv64; other\narchitectures (e.g. s390x, x86, powerpc) never get a TARGET\u003d line.\n\nTherefore the grep result will be empty, and the config_export() prints an\n`export` into the generated standalone script. Which dumps every currently\nexported variable to stdout.\n\nFix config_export() to skip emitting anything when the requested\nvariable isn\u0027t present in config.mak.\n\nSigned-off-by: Po-Hsu Lin \u003cpo-hsu.lin@canonical.com\u003e\n" }, { "commit": "8bf102b93eecf879a2313cc30beef88e00f140d7", "tree": "cee185da0ee0d09eecfcb496721d02701d9843e1", "parents": [ "402e81d2208edef5248515f3d228783eddf3160a" ], "author": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Tue Aug 04 11:55:37 2026 +0000" }, "committer": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Mon Aug 24 11:45:38 2026 +0000" }, "message": "s390x: skey: Fence TCG protection checks\n\nTCG does not implement the skey memory protection, skip those tests\nunder TCG instead of filtering them in the CI logs.\n\nThis way the test will PASS when run by humans and there\u0027s no\nconfusion why it fails anymore.\n\nSigned-off-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\n" }, { "commit": "402e81d2208edef5248515f3d228783eddf3160a", "tree": "4964e42fd4121eea6f92205162a845e6fb88f5d0", "parents": [ "463c13865f2a38893991e25e172d1113ac9a9614" ], "author": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Tue Aug 04 11:20:18 2026 +0000" }, "committer": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Mon Aug 24 11:45:30 2026 +0000" }, "message": "s390x: unittests: Reenable tcg for migration tests\n\nThe TCG fixes for this issue have been in QEMU for quite a while.\nIt\u0027s time to reenable these tests.\n\nQEMU fix discussion:\nhttps://lore.kernel.org/qemu-devel/20240312201458.79532-1-philmd@linaro.org/\n\nSigned-off-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\n" }, { "commit": "463c13865f2a38893991e25e172d1113ac9a9614", "tree": "8255b40edd7326278f31f951abdc228959c43a0c", "parents": [ "6f7357d6d73e1b7f951d9e1ed59beb84954e1007" ], "author": { "name": "Christian Borntraeger", "email": "borntraeger@linux.ibm.com", "time": "Mon Jun 29 11:19:21 2026 +0200" }, "committer": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Mon Aug 24 11:45:05 2026 +0000" }, "message": "s390x: stsi: regression test for the STSI 3.2.2 count clamp\n\nSee https://lore.kernel.org/qemu-devel/20260622092035.400959-1-borntraeger@linux.ibm.com/\nfor the QEMU fix.\nAdd a regression test that races STSI 3.2.2 on one CPU against a second CPU\nthat continuously forces an out-of-range count value.\nThe out of bound access usually crashes/asserts QEMU with any sane\ndistribution build of QEMU, so its more or less guest root can kill itself.\nWe should test and fix nevertheless.\nTestcase piggybacks on the existing stsi test, so some cases will be\ntested twice. (with smp 1 and smp 2)\n\nSigned-off-by: Christian Borntraeger \u003cborntraeger@linux.ibm.com\u003e\nCc: Cornelia Huck \u003ccohuck@redhat.com\u003e\nReviewed-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\nReviewed-by: Cornelia Huck \u003ccohuck@redhat.com\u003e\n[frankja@linux.ibm.com: Merged the new unittests.cgf entry into old one]\nSigned-off-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\n" }, { "commit": "6f7357d6d73e1b7f951d9e1ed59beb84954e1007", "tree": "227cff49dd0d59238be1eade97eb8d3bd8cfb8c5", "parents": [ "7186ae24436ec590d98050e72201d5be56337ce2" ], "author": { "name": "Christoph Schlameuss", "email": "schlameuss@linux.ibm.com", "time": "Tue Apr 21 10:11:23 2026 +0200" }, "committer": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Mon Aug 24 11:44:53 2026 +0000" }, "message": "s390x: Add test for STFLE interpretive execution (format-2)\n\nThe STFLE instruction indicates installed facilities.\nSIE has facilities for the interpretive execution of STFLE.\nThere are multiple possible formats for the control block.\nUse a snippet guest executing STFLE to get the result of\ninterpretive execution and check the result.\nWith the addition of the format-2 control block invalid format\nspecifiers are now possible.\nTest for the occurrence of optional validity intercepts.\n\nMove prefixes into main method to improve the readability of the\nlog by having prefixes for reports by tests called from multiple\nplaces.\n\nCo-developed-by: Nina Schoetterl-Glausch \u003cnsg@linux.ibm.com\u003e\nSigned-off-by: Nina Schoetterl-Glausch \u003cnsg@linux.ibm.com\u003e\nSigned-off-by: Christoph Schlameuss \u003cschlameuss@linux.ibm.com\u003e\nReviewed-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\nSigned-off-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\n" }, { "commit": "7186ae24436ec590d98050e72201d5be56337ce2", "tree": "a32b5af446286c79641498b0e4d87dbbcb5d257d", "parents": [ "b1c5d74ff45c4be6470db5bbd4895e77d8c9f277" ], "author": { "name": "Nina Schoetterl-Glausch", "email": "nsg@linux.ibm.com", "time": "Wed Nov 22 18:54:34 2023 +0100" }, "committer": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Mon Aug 24 11:44:23 2026 +0000" }, "message": "s390x: sclp: Add detection of alternate STFLE facilities\n\nDetect availability of alternate STFLE interpretive execution facilities\n1 and 2.\n\nSigned-off-by: Nina Schoetterl-Glausch \u003cnsg@linux.ibm.com\u003e\nCo-developed-by: Christoph Schlameuss \u003cschlameuss@linux.ibm.com\u003e\nReviewed-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\nSigned-off-by: Christoph Schlameuss \u003cschlameuss@linux.ibm.com\u003e\nSigned-off-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\n" }, { "commit": "b1c5d74ff45c4be6470db5bbd4895e77d8c9f277", "tree": "dc01aaa5708fbded5e18966ecfb14af92a974979", "parents": [ "111e1e4915ed12e57ead334116f28e4463e0c183" ], "author": { "name": "Christoph Schlameuss", "email": "schlameuss@linux.ibm.com", "time": "Fri Apr 17 17:34:35 2026 +0200" }, "committer": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Mon Aug 24 11:43:46 2026 +0000" }, "message": "s390x: sclp: Use sclp_feat_check directly to read DIAG318 feature bit\n\nThe additional entry in struct ReadInfo is only used to set sclp_facilities\nwhere we are aware where these bits actually are in _read_info. So it is\nmore readable to directly check the bit here.\n\nWhile at it order feat checks by byte and bit.\n\nReviewed-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\nReviewed-by: Nico Boehr \u003cnrb@linux.ibm.com\u003e\nSigned-off-by: Christoph Schlameuss \u003cschlameuss@linux.ibm.com\u003e\nSigned-off-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\n" }, { "commit": "111e1e4915ed12e57ead334116f28e4463e0c183", "tree": "6d63dd03fee9f528ad757c37f5b3dc2a1233f507", "parents": [ "d9433b57acf4d2234dc2ae1dad508be0941a004d" ], "author": { "name": "Christoph Schlameuss", "email": "schlameuss@linux.ibm.com", "time": "Wed Apr 22 16:42:45 2026 +0200" }, "committer": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Mon Aug 24 11:43:17 2026 +0000" }, "message": "s390x: sclp: Check sclp byte before reading feature bits\n\nImprove the readability and simplicity of the code in\nsclp_facilities_setup() by moving the check for availabity of feature bits\ninto sclp_feat_check().\n\nSuggested-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\nReviewed-by: Nico Boehr \u003cnrb@linux.ibm.com\u003e\nSigned-off-by: Christoph Schlameuss \u003cschlameuss@linux.ibm.com\u003e\nSigned-off-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\n" }, { "commit": "d9433b57acf4d2234dc2ae1dad508be0941a004d", "tree": "9f53cb967a460abc91f88064ca99be7e774bd7e0", "parents": [ "4a98dad524b9fd7e1a43c0194d9941990d3c1aea" ], "author": { "name": "Christoph Schlameuss", "email": "schlameuss@linux.ibm.com", "time": "Fri Feb 20 12:33:54 2026 +0100" }, "committer": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Mon Aug 24 11:42:46 2026 +0000" }, "message": "s390x: sclp: Remove unnecessary padding from struct sclp_facilities\n\nStruct sclp_facilities is only used within the guest to keep the facility\ninformation. Nothing bad should happen when the struct size changes in the\nfuture.\n\nSuggested-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\nSigned-off-by: Christoph Schlameuss \u003cschlameuss@linux.ibm.com\u003e\nReviewed-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\nReviewed-by: Nico Boehr \u003cnrb@linux.ibm.com\u003e\nSigned-off-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\n" }, { "commit": "4a98dad524b9fd7e1a43c0194d9941990d3c1aea", "tree": "d0f3f0efe197b3d3cb673d2df00fea326a7bcc37", "parents": [ "93e5a59e0299f857ce08297ac0af9fcd392cd280" ], "author": { "name": "Nina Schoetterl-Glausch", "email": "nsg@linux.ibm.com", "time": "Wed Nov 22 18:50:03 2023 +0100" }, "committer": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Mon Aug 24 11:40:47 2026 +0000" }, "message": "s390x: snippets: Add reset_guest() to lib\n\nExtract reset_guest from spec_ex-sie into the lib.\nAfter reset_guest() the snippet can be executed again.\n\nSigned-off-by: Nina Schoetterl-Glausch \u003cnsg@linux.ibm.com\u003e\nSigned-off-by: Christoph Schlameuss \u003cschlameuss@linux.ibm.com\u003e\nReviewed-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\nReviewed-by: Nico Boehr \u003cnrb@linux.ibm.com\u003e\nSigned-off-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\n" }, { "commit": "93e5a59e0299f857ce08297ac0af9fcd392cd280", "tree": "f1a01d93e2f54fe86477913caab307af7ec0c75b", "parents": [ "8cdd0eca44982ae810f308bdd57e7a3e423d203c" ], "author": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Tue Dec 02 13:21:13 2025 +0000" }, "committer": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Tue Aug 04 11:38:21 2026 +0000" }, "message": "lib: s390x: snippet: Add function to create a guest of specific length\n\nWhile 1MB is certainly enough to store the guest code, it\u0027s often not\nenough for memory tests. Let\u0027s add a separate function to allow\narbitrary guest sizes.\n\nSigned-off-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\nReviewed-by: Nico Boehr \u003cnrb@linux.ibm.com\u003e\nReviewed-by: Christoph Schlameuss \u003cschlameuss@linux.ibm.com\u003e\n" }, { "commit": "8cdd0eca44982ae810f308bdd57e7a3e423d203c", "tree": "81936d73a3714b9af71af1d8436da5811baf7eb9", "parents": [ "08cb3baf2ee196f05950966cb4852c8f49c8cfd3" ], "author": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Mon Dec 01 15:30:55 2025 +0000" }, "committer": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Tue Aug 04 11:38:18 2026 +0000" }, "message": "lib: s390x: sie: Memory rework\n\nMake sie_guest_create() directly alloc the guest\u0027s memory.\n\nAlso we never freed the memory that the sie library allocates as the guest\nram on destruction of the VM. Most tests reuse the VM or just leak the\nmemory since the standard allocation is one megabyte and tests only\nuse single digit numbers of VMs.\n\nIt\u0027s time to add automatic freeing to the sie library when a VM is\ndestroyed.\n\nSigned-off-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\nReviewed-by: Christoph Schlameuss \u003cschlameuss@linux.ibm.com\u003e\n" }, { "commit": "08cb3baf2ee196f05950966cb4852c8f49c8cfd3", "tree": "ac158c03b127a6833b7e9dd108d7178131cac786", "parents": [ "cb9bdbf3b77ff67687567692dc2191bef470b6da" ], "author": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Mon Dec 01 15:30:32 2025 +0000" }, "committer": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Tue Aug 04 11:37:55 2026 +0000" }, "message": "lib: s390x: sie: Allocate physical guest memory via memalign\n\nalloc_pages_flags() alignes the allocation on the same order as its\nrequested size. Since we use virtual memory for SIE we can instead\nalign to 1MB by using memalign() which is less wasteful.\n\nSigned-off-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\nReviewed-by: Christoph Schlameuss \u003cschlameuss@linux.ibm.com\u003e\nReviewed-by: Nico Boehr \u003cnrb@linux.ibm.com\u003e\n" }, { "commit": "cb9bdbf3b77ff67687567692dc2191bef470b6da", "tree": "d0584a42ff2d4156843df107f27edbbd66111cec", "parents": [ "f20b0b8d3373ab489ef3ed9f2ebdf6839bcddd9c" ], "author": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Mon Dec 01 15:16:49 2025 +0000" }, "committer": { "name": "Janosch Frank", "email": "frankja@linux.ibm.com", "time": "Tue Aug 04 11:37:53 2026 +0000" }, "message": "lib: s390x: Add function to get page root\n\nIt\u0027s time to hide the access to cr1 behind a function and add typing\nto the tests that used void* instead of pgdt_t*.\n\nSigned-off-by: Janosch Frank \u003cfrankja@linux.ibm.com\u003e\nReviewed-by: Christoph Schlameuss \u003cschlameuss@linux.ibm.com\u003e\nReviewed-by: Nico Boehr \u003cnrb@linux.ibm.com\u003e\n" }, { "commit": "f20b0b8d3373ab489ef3ed9f2ebdf6839bcddd9c", "tree": "31307176a3aa624419ec3f8b7b8ab7781e41849e", "parents": [ "033ab80d18bca31a6e428b877518883c90c3a2aa" ], "author": { "name": "Colton Lewis", "email": "coltonlewis@google.com", "time": "Thu Jul 16 17:33:15 2026 +0000" }, "committer": { "name": "Andrew Jones", "email": "andrew.jones@linux.dev", "time": "Tue Jul 21 10:56:15 2026 +0200" }, "message": "Makefile: efi: preserve .dynstr section for LLVM objcopy compatibility\n\nWhen building EFI binaries with llvm-objcopy, keeping sections with\n\u0027-j .dynamic -j .dynsym\u0027 without \u0027-j .dynstr\u0027 fails with:\n\n llvm-objcopy: error: \u0027arm/spinlock-test.so\u0027: section \u0027.dynstr\u0027\n cannot be removed because it is referenced by the section \u0027.dynamic\u0027\n\nInclude \u0027.dynstr\u0027 in the list of preserved sections across\narm/Makefile.common, riscv/Makefile, and x86/Makefile.common so that\nEFI binaries can be built cleanly using llvm-objcopy.\n\nAssisted-by: Gemini:gemini-next\nSigned-off-by: Colton Lewis \u003ccoltonlewis@google.com\u003e\nSigned-off-by: Andrew Jones \u003candrew.jones@linux.dev\u003e\n" }, { "commit": "033ab80d18bca31a6e428b877518883c90c3a2aa", "tree": "9635614884f5a4bc5418e0aea053bdfd709cdda1", "parents": [ "8f2ac2697df242a17fcc76fff1a235c09e6bfc68" ], "author": { "name": "Nicholas Piggin", "email": "npiggin@gmail.com", "time": "Sun Jul 19 18:30:27 2026 +0530" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon Jul 20 08:27:29 2026 +0200" }, "message": "powerpc: Add a panic test\n\nThis adds a simple panic test for pseries that works with\nTCG (unlike the s390x panic tests), making it easier to test\nthis part of the harness code.\n\nSigned-off-by: Nicholas Piggin \u003cnpiggin@gmail.com\u003e\nReviewed-by: Thomas Huth \u003cthuth@redhat.com\u003e\nSigned-off-by: Chinmay Rath \u003crathc@linux.ibm.com\u003e\nMessage-ID: \u003c20260719130027.2347519-7-rathc@linux.ibm.com\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "8f2ac2697df242a17fcc76fff1a235c09e6bfc68", "tree": "ff18c41d239f1b46c0738405ffe1ce4db77a9890", "parents": [ "1731a7ed50027efe18773e84ebad910edb8f4180" ], "author": { "name": "Nicholas Piggin", "email": "npiggin@gmail.com", "time": "Sun Jul 19 18:30:26 2026 +0530" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon Jul 20 08:27:28 2026 +0200" }, "message": "scripts/arch-run.bash: Fix run_panic() success exit status\n\nrun_qemu_status() looks for \"EXIT: STATUS\u003d%d\" if the harness command\nreturned 1, to determine the final status of the test. In the case of\npanic tests, QEMU should terminate before successful exit status is\nknown, so the run_panic() command must produce the \"EXIT: STATUS\" line.\n\nWith this change, running a panic test returns 0 on success (panic),\nand the run_test.sh unit test correctly displays it as PASS rather than\nFAIL.\n\nSigned-off-by: Nicholas Piggin \u003cnpiggin@gmail.com\u003e\nAcked-by: Andrew Jones \u003candrew.jones@linux.dev\u003e\nSigned-off-by: Chinmay Rath \u003crathc@linux.ibm.com\u003e\nMessage-ID: \u003c20260719130027.2347519-6-rathc@linux.ibm.com\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "1731a7ed50027efe18773e84ebad910edb8f4180", "tree": "f4c87c428d172e3b8d8c4019016308b89ec4df2f", "parents": [ "1cd967b4d3ba1bbba1be9043b474745d9b926c4e" ], "author": { "name": "Nicholas Piggin", "email": "npiggin@gmail.com", "time": "Sun Jul 19 18:30:25 2026 +0530" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon Jul 20 08:27:28 2026 +0200" }, "message": "powerpc: gitlab CI update\n\nAdds a few additional tests that are known to work in CI.\n\nTo control overhead, ppc64be is used to test 64k page size, ppc64le is\nused to test 4k page size.\n\nSigned-off-by: Nicholas Piggin \u003cnpiggin@gmail.com\u003e\nSigned-off-by: Chinmay Rath \u003crathc@linux.ibm.com\u003e\nMessage-ID: \u003c20260719130027.2347519-5-rathc@linux.ibm.com\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "1cd967b4d3ba1bbba1be9043b474745d9b926c4e", "tree": "4c0773b22cf244b3e0c7d58faa702a1fa195514f", "parents": [ "28e908519b5c577999af970d89c06714f162d7ad" ], "author": { "name": "Nicholas Piggin", "email": "npiggin@gmail.com", "time": "Sun Jul 19 18:30:24 2026 +0530" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon Jul 20 08:27:28 2026 +0200" }, "message": "powerpc: Remove remnants of ppc64 directory and build structure\n\nThis moves merges ppc64 directories and files into powerpc, and\nmerges the 3 makefiles into one.\n\nThe configure --arch\u003dpowerpc option is aliased to ppc64 for\ngood measure.\n\nAcked-by: Thomas Huth \u003cthuth@redhat.com\u003e\nSigned-off-by: Nicholas Piggin \u003cnpiggin@gmail.com\u003e\nSigned-off-by: Chinmay Rath \u003crathc@linux.ibm.com\u003e\nMessage-ID: \u003c20260719130027.2347519-4-rathc@linux.ibm.com\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "28e908519b5c577999af970d89c06714f162d7ad", "tree": "d017b9ece4d35a213e4becf4ecf7ad7b3fbac6fd", "parents": [ "73d64c56bb74cc803bd47ae6e7eca04fe2e4302d" ], "author": { "name": "Nicholas Piggin", "email": "npiggin@gmail.com", "time": "Sun Jul 19 18:30:23 2026 +0530" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon Jul 20 08:27:28 2026 +0200" }, "message": "configure: Make arch_libdir a first-class entity\n\narch_libdir was brought in to improve the heuristic determination of\nthe lib/ directory based on arch and testdir names, but it did not\nentirely clean that mess up.\n\nRemove the arch_libdir-\u003earch-\u003etestdir heuristic and just require\neverybody sets arch_libdir correctly. Fail if the lib/arch or\nlib/arch/asm directories can not be found.\n\nSigned-off-by: Nicholas Piggin \u003cnpiggin@gmail.com\u003e\nReviewed-by: Andrew Jones \u003candrew.jones@linux.dev\u003e\nSigned-off-by: Chinmay Rath \u003crathc@linux.ibm.com\u003e\nMessage-ID: \u003c20260719130027.2347519-3-rathc@linux.ibm.com\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "73d64c56bb74cc803bd47ae6e7eca04fe2e4302d", "tree": "775549513aeb5ffac0dc2c3fdc42d0ad32290f25", "parents": [ "1da1819e49fc4938985edca67df669099b4c87a7" ], "author": { "name": "Nicholas Piggin", "email": "npiggin@gmail.com", "time": "Sun Jul 19 18:30:22 2026 +0530" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon Jul 20 08:27:28 2026 +0200" }, "message": "powerpc: add pmu tests\n\nAdd some initial PMU testing.\n\n- PMC5/6 tests\n- PMAE / PMI test\n- BHRB basic tests\n\nSigned-off-by: Nicholas Piggin \u003cnpiggin@gmail.com\u003e\nSigned-off-by: Chinmay Rath \u003crathc@linux.ibm.com\u003e\nMessage-ID: \u003c20260719130027.2347519-2-rathc@linux.ibm.com\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "1da1819e49fc4938985edca67df669099b4c87a7", "tree": "bbff2020a0f6cafde7d5da8d00ca7bd5f7834539", "parents": [ "6b9c3507452cad609be23d7383525432895ea860", "1ee88e4573e280831f4ce21f12f0282e7f10aafb" ], "author": { "name": "Andrew Jones", "email": "andrew.jones@linux.dev", "time": "Fri Jun 26 16:46:29 2026 +0200" }, "committer": { "name": "Andrew Jones", "email": "andrew.jones@linux.dev", "time": "Fri Jun 26 16:46:29 2026 +0200" }, "message": "Merge branch \u0027arm/queue\u0027 into \u0027master\u0027\n\narm64: A fix and EL2 prep\n\nSee merge request kvm-unit-tests/kvm-unit-tests!87" }, { "commit": "1ee88e4573e280831f4ce21f12f0282e7f10aafb", "tree": "bbff2020a0f6cafde7d5da8d00ca7bd5f7834539", "parents": [ "a3150b8dadde75e858025c25d47a06819a205d71" ], "author": { "name": "Joey Gouly", "email": "joey.gouly@arm.com", "time": "Wed Apr 22 14:08:20 2026 +0100" }, "committer": { "name": "Andrew Jones", "email": "andrew.jones@linux.dev", "time": "Fri Jun 26 09:31:49 2026 -0500" }, "message": "arm64: update ESR_ELx definitions to match Linux kernel\n\nkvm-unit-test supports EL2, so replace the ESR_EL1* names with ESR_ELx.\n\nThis section was copied from arch/arm64/include/asm/esr.h, as was the previous\ncontents of the file.\n\nSigned-off-by: Joey Gouly \u003cjoey.gouly@arm.com\u003e\nCc: Jing Zhang \u003cjingzhangos@google.com\u003e\nReviewed-by: Jing Zhang \u003cjingzhangos@google.com\u003e\nSigned-off-by: Andrew Jones \u003candrew.jones@linux.dev\u003e\n" }, { "commit": "a3150b8dadde75e858025c25d47a06819a205d71", "tree": "5b8b82dc0ee403c6d4e6f90d0d5dfbd5caec2489", "parents": [ "6b9c3507452cad609be23d7383525432895ea860" ], "author": { "name": "Colton Lewis", "email": "coltonlewis@google.com", "time": "Fri Jun 19 00:25:04 2026 +0000" }, "committer": { "name": "Andrew Jones", "email": "andrew.jones@linux.dev", "time": "Fri Jun 26 09:15:19 2026 -0500" }, "message": "arm: io: Set is_pl011_uart flag in ACPI initialization\n\nWhen booting via ACPI on ARM64, the SPCR table is parsed to initialize\nthe console UART. However, the code was neglecting to set the\nis_pl011_uart flag. This caused __getchar() to fall back to treating\nthe UART as a 16550A device, which fails on systems with a PL011.\n\nTests that wait for serial input (like its-migration) would hang\nindefinitely because __getchar() would always return -1.\n\nUpdate uart0_init_acpi() to inspect the SPCR interface_type and set\nis_pl011_uart accordingly. Also define DBG2 macros for SPCR\ninterface types in lib/acpi.h.\n\nLink: https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/acpi-debug-port-table#table-3-debug-port-types-and-subtypes\nFixes: 8c065edf33c0 (\"lib/arm/io: Fix calling getchar() multiple times\")\nReviewed-by: Alexandru Elisei \u003calexandru.elisei@arm.com\u003e\nAssisted-by: Gemini:gemini-3.1-pro\nSigned-off-by: Colton Lewis \u003ccoltonlewis@google.com\u003e\nSigned-off-by: Andrew Jones \u003candrew.jones@linux.dev\u003e\n" }, { "commit": "6b9c3507452cad609be23d7383525432895ea860", "tree": "2898b647ce72d133e7ecd0c0ad49f958a49a1efc", "parents": [ "1647129fd9b69f173f059b94a29667adfc7e0015" ], "author": { "name": "Andrew Jones", "email": "andrew.jones@linux.dev", "time": "Mon Jun 22 11:31:39 2026 -0500" }, "committer": { "name": "Andrew Jones", "email": "andrew.jones@linux.dev", "time": "Fri Jun 26 09:14:12 2026 -0500" }, "message": "checkpatch: add support for Assisted-by tag\n\nImport Linux commit d1db4118489f (\"checkpatch: add support for\nAssisted-by tag\").\n\n(I should have used AI for this, since it\u0027d be fun to include that\ntag on this tag-enabling patch, but sometimes I still do my own\nhomework!)\n\nSigned-off-by: Andrew Jones \u003candrew.jones@linux.dev\u003e\n" }, { "commit": "1647129fd9b69f173f059b94a29667adfc7e0015", "tree": "f7f901d940ddd046737de0578bef0dd8c412c258", "parents": [ "afcc98a30a84aaefc1f0d6783ffffec16c736717", "87ddaa8b5b374ac0049da4220c87dfe81ec1c8a7" ], "author": { "name": "Paolo Bonzini", "email": "bonzini@gnu.org", "time": "Mon Jun 22 12:43:13 2026 +0000" }, "committer": { "name": "Paolo Bonzini", "email": "bonzini@gnu.org", "time": "Mon Jun 22 12:43:13 2026 +0000" }, "message": "Merge branch \u002732bit\u0027 into \u0027master\u0027\n\nadd 32 bit nested guest tests and non-NPT SVM tests\n\nSee merge request kvm-unit-tests/kvm-unit-tests!86" }, { "commit": "87ddaa8b5b374ac0049da4220c87dfe81ec1c8a7", "tree": "f7f901d940ddd046737de0578bef0dd8c412c258", "parents": [ "ed8d5c638df739e2e663da2a3d58f89b8006c603" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Mon Jun 22 07:26:59 2026 -0400" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Mon Jun 22 07:26:59 2026 -0400" }, "message": "svm_tests: replace rdpru with byte encoding\n\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "ed8d5c638df739e2e663da2a3d58f89b8006c603", "tree": "6826e0a6c4a04d25c0b0eec8ded291c967047d3a", "parents": [ "ee6f16210028d509492e14a485ae239719c4a1f0" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Wed May 20 15:36:47 2026 +0200" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Mon Jun 22 07:23:58 2026 -0400" }, "message": "svm: add test for 32-bit non-PAE guest\n\nVMX tests are only running 64-bit guests. Add a test that checks\nthe reserved and ignored bits in CR3 for legacy two-level paging.\n\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "ee6f16210028d509492e14a485ae239719c4a1f0", "tree": "c01efea26af02d545b7a852536a6a04e6b50fd46", "parents": [ "feef9d927818346f6deb4c71f15313109f746aae" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 10:53:41 2026 +0200" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Mon Jun 22 07:23:58 2026 -0400" }, "message": "svm: add test for 32-bit PAE guest\n\nSVM tests are only running 64-bit guests. Add a test that checks\nthe reserved and ignored bits in CR3 and PDPTEs for PAE mode.\n\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "feef9d927818346f6deb4c71f15313109f746aae", "tree": "36b9314fd265964d25350095d9220e9b90078b33", "parents": [ "55b77db17a76aa69dd1b82926fe4ac779531cbe7" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu Jun 04 10:26:17 2026 +0200" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Mon Jun 22 07:23:58 2026 -0400" }, "message": "vmx: add test for 32-bit non-PAE guest\n\nVMX tests were only running 64-bit guests. Add a test that checks\nthe reserved and ignored bits in CR3 for legacy 2-level page tables.\n\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "55b77db17a76aa69dd1b82926fe4ac779531cbe7", "tree": "27a70a86f935c61c297acb9030327c5510e5a025", "parents": [ "e212ec59273fbc9c6aad7c66661f8dcd227b70d4" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu Jun 04 09:24:12 2026 +0200" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Mon Jun 22 07:23:58 2026 -0400" }, "message": "vmx: add a test for 32-bit guest PAE paging PDPTEs\n\nVMX tests are only running 64-bit guests. Add a test that checks\nthe reserved and ignored bits in CR3 and PDPTEs for PAE mode.\n\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "e212ec59273fbc9c6aad7c66661f8dcd227b70d4", "tree": "0ee370946e390075bcdbd1d1c812c663f343266c", "parents": [ "afcc98a30a84aaefc1f0d6783ffffec16c736717" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:33:50 2026 +0200" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Mon Jun 22 13:21:28 2026 +0200" }, "message": "unittests.cfg: add an entry to run SVM tests with NPT disabled\n\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "afcc98a30a84aaefc1f0d6783ffffec16c736717", "tree": "5160a4296e9f9b249ebab1812cdee8b3b564a5a3", "parents": [ "0f098eada6b0d2eda06e6c4fcde49e8a9107df6b" ], "author": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Thu Jun 11 08:52:34 2026 +0200" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Thu Jun 11 08:52:34 2026 +0200" }, "message": "Remove the Fedora Cirrus-CI job\n\nCirrus-CI has been shut down at the beginning of June 2026, so\nremove the defunct Fedora Cirrus-CI job now.\n\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "0f098eada6b0d2eda06e6c4fcde49e8a9107df6b", "tree": "7da7eaeb1e901377ff9a5c9fdedf75239b540455", "parents": [ "05b7715ffd4ae4ef8f0a5dea869f1543d89f936d", "c10d4616e2ad5d95553b2f0c389b4546dfacd76f" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Sat May 30 13:11:17 2026 -0400" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Sat May 30 13:11:17 2026 -0400" }, "message": "Merge tag \u0027kvm-x86-2026.05.27\u0027 of https://github.com/kvm-x86/kvm-unit-tests into HEAD\n\nKVM-Unit-Tests x86 changes:\n\n - Track SVM\u0027s EXIT_CODE as a 64-bit value, to verify KVM does the same.\n\n - Add nSVM tests for unsupported instruction intercepts.\n\n - Serialize the (v)CPU after WRMSR(TSCDEADLINE) to prepare for APIC timer\n virtualization.\n\n - Disable PKU in the vCPU model when running the nVMX access tests to make\n the runtime somewhat reasonable.\n\n - Extended the VMOVDQA test to cover VMOVNTDQA as well.\n\n - Add test coverage for ENTER + emulated MMIO.\n\n - Misc fixes, cleanups, and minor coverage enhancements.\n" }, { "commit": "c10d4616e2ad5d95553b2f0c389b4546dfacd76f", "tree": "9452fb8dc7b9982f070af3be2fd3e03b603c8347", "parents": [ "20693e433cc155af5ba46be1c23204cd55e03ceb" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Wed May 27 08:23:33 2026 -0700" }, "committer": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Wed May 27 08:59:46 2026 -0700" }, "message": "x86/vmx: Remove the superfluous vmx_cet config entry\n\nDrop the dedicated configuration entry for vmx_cet as the test is NOT\nexcluded from the main \"vmx\" config, i.e. it\u0027s already being run by the\nmain config (and thus obviously doesn\u0027t need a timeout of 240 seconds).\n\nLink: https://patch.msgid.link/20260527152333.4062942-1-seanjc@google.com\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "20693e433cc155af5ba46be1c23204cd55e03ceb", "tree": "7d804b08a9cf7064441b2a293edab11eda1f1080", "parents": [ "c490a16fe1caf709653187e1dc7a60a8d2a3340c" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:15:10 2026 -0700" }, "committer": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Wed May 27 08:45:34 2026 -0700" }, "message": "x86/emulator: Add testcases for ENTER + emulated MMIO\n\nAdd testcases for stack pushes to emulated MMIO via the ENTER instruction\nto validate a pile of KVM changes needed to fix a use-after-free due to\nKVM referencing kernel stack data across a userspace exit. Test that ENTER\nis handled correctly if it splits non-MMIO \u003d\u003e MMIO, MMIO \u003d\u003e non-MMIO, and\nMMIO \u003d\u003e MMIO pages.\n\nOpportunistically add a comment explaining what the collection of pages\nare used for in the emulator test.\n\nLink: https://lore.kernel.org/all/20260225012049.920665-1-seanjc@google.com\nLink: https://patch.msgid.link/20260514211510.1630673-1-seanjc@google.com\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "c490a16fe1caf709653187e1dc7a60a8d2a3340c", "tree": "c7337ad97aa97762a4d4a5bcffb7a3222a8c3d8e", "parents": [ "027ea799b8593cd5d09059fdfcb888d49bedbcfa" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:07:08 2026 -0700" }, "committer": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Wed May 27 08:37:00 2026 -0700" }, "message": "x86/apic: Verify LVT timer register mode reads back what was written\n\nReport a failure (but not a pass, for brevity) if an APIC timer mode change\nreads back a different mode than was written, e.g. to verify that LVTT\nreads via x2APIC MSR are accelerated by hardware and access the backing\npage when APICv/x2AVIC is enabled.\n\nCc: Naveen N Rao (AMD) \u003cnaveen@kernel.org\u003e\nLink: https://patch.msgid.link/20260514210708.1627866-1-seanjc@google.com\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "027ea799b8593cd5d09059fdfcb888d49bedbcfa", "tree": "e6d7b896b819f7fea053729ddc9d8ff87685accd", "parents": [ "01a2f542c4b8e7cd96fc806fe22c0f124365e0f1" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:12:37 2026 -0700" }, "committer": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Wed May 27 08:37:00 2026 -0700" }, "message": "x86/debug: Verify DR6 is always empty on an INT1/ICEBP #DB\n\nExtend the single-step + INT/ICEBP #DB testcase to verify that DR6.BS\u003d\u003d0\non the ICEBP #DB, even when single-step is fully enabled. Per the SDM:\n\n The INT1 instruction also uses a one-byte opcode (F1) and generates a\n debug exception (#DB) without setting any bits in DR6.\n\nLink: https://patch.msgid.link/20260514211237.1629774-1-seanjc@google.com\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "01a2f542c4b8e7cd96fc806fe22c0f124365e0f1", "tree": "d31c03fe6d1c92325276a54d3a47492376e491a6", "parents": [ "7e7d2f89232b062c506dd4b8235cd7b08ed2e615" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 13:40:20 2026 -0700" }, "committer": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Wed May 27 08:37:00 2026 -0700" }, "message": "x86/xsave: Extend VMOVDQA testing to also cover VMOVNTDQA\n\nExtend the XSAVE test\u0027s VMOVDQA coverage to also validate KVM\u0027s recently\nadded (and initially broken) emulation of VMOVNTDQA instructions. Despite\nthe seemingly generic and all-too-similar names, VMOVNTDQ and VMOVNTDQA\nare unidirectional instructions with opposite semantics: VMOVNTDQ *always*\nstores to memory, whereas VMOVNTDQA *always* loads from memory.\n\nRework the checking to use a buffer that is never written as part of the\ntestcase itself for the source of truth. KVM\u0027s bug was that it mixed up\nthe direction of VMOVNTDQA, i.e. KVM was loading from registers and storing\nto memory. Comparing the src and dst buffers on a:\n\n src \u003d\u003e reg \u003d\u003e dst\n\nsequence won\u0027t detect mismatches due to such bugs, i.e. if KVM wrongly\ndoes:\n\n reg \u003d\u003e src, reg \u003d\u003e dst\n\necause by the end, src \u003d\u003d dst, but with the wrong values.\n\nLink: https://patch.msgid.link/20260514204020.1614792-1-seanjc@google.com\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "7e7d2f89232b062c506dd4b8235cd7b08ed2e615", "tree": "f20160e9c99095185277ddb443d9bd2b6123312b", "parents": [ "74af64ed61b91dd623c87a9e329bf024ff0c97ab" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 13:05:36 2026 -0700" }, "committer": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Wed May 27 08:37:00 2026 -0700" }, "message": "x86: Disable PKU in vCPU model for vmx_pf_{vpid/no_vpid/invvpid}_test\n\nRun the vmx_pf_{vpid/no_vpid/invvpid}_test VMX tests with -pku, i.e. with\nProtection Keys disabled in the (v)CPU model, to reduce the number of\ntestcases by an order of magnitude, which in turn reduces the runtime by\nroughly the same factor. As is, even the 240 seconds timeout is\ninsufficient, e.g. each test can take upwards of 300 seconds when run on\nSkylake-era hardware with a debug kernel.\n\nSimply disable PKU in the config as the purpose of the VMX #PF tests is\nprimarily to validate #PF routing (to L1 vs. L0), and secondarily to\nvalidate alternative TLB flushing mechanisms, e.g. INVVPID. The only\nnovelty provided by PKU with respect to those goals is an additional\nflag in the #PF error code, and the odds of KVM botching _only the PKU\nflag when routing #PFs is very low.\n\nDisable PKU in the config, e.g. instead of passing a param from the test,\nso that the test can be run with PKU enabled simply by tweaking the QEMU\ncommand line, e.g. without recompiling.\n\nReported-by: Yosry Ahmed \u003cyosry@kernel.org\u003e\nReviewed-by: Yosry Ahmed \u003cyosry@kernel.org\u003e\nLink: https://patch.msgid.link/20260514200536.1603737-1-seanjc@google.com\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "74af64ed61b91dd623c87a9e329bf024ff0c97ab", "tree": "7db851ca294505e06351d63c3526c489c4f1f532", "parents": [ "dc1403530fdc00d0efd1011868e6a3e598618201" ], "author": { "name": "Isaku Yamahata", "email": "isaku.yamahata@intel.com", "time": "Thu Mar 05 09:47:53 2026 -0800" }, "committer": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Wed May 27 08:37:00 2026 -0700" }, "message": "x86: tscdeadline_latency: Remove unnecessary nop\n\nEliminate unncessary nop instruction right after wrmsr(TSC DEADLINE) for\ncode clarity.\n\nThe existing logic is sti(), wrmsr(TSC DEADLINE), NOP, and loop HLT to wait\nfor the interrupts. Because we explicitly wait for the timer interrupts\nwith the interrupt unmasked, the test doesn\u0027t need the NOP instruction to\nbe a place where the interrupt is raised. Other tests (apic and vmexit)\nexpect that the timer interrupt happens right after wrmsr(TSC DEADLINE),\nwhich needs the interruptible window and serialization right after updating\nthe deadline value. However, tscdeadline_latency doesn\u0027t need it. Delete\nthe unnecessary NOP to clarify that serialization isn\u0027t needed.\n\nThe code doesn\u0027t have any comments on why NOP is there. The commit message\nof d482c49772fb (\"kvm-unit-tests: add tscdeadline-latency test\") has only\n\"To test latency between TSC deadline timer interrupt injection.\", which\ndoesn\u0027t tell why. The following commits that modify the file doesn\u0027t touch\nNOP.\n\nSigned-off-by: Isaku Yamahata \u003cisaku.yamahata@intel.com\u003e\nLink: https://patch.msgid.link/2ef8af4c0afc26feee8a993ef818f9ed40a7f329.1772678359.git.isaku.yamahata@intel.com\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "dc1403530fdc00d0efd1011868e6a3e598618201", "tree": "bfd221d6ae4a2544c711a8100d18940316e7116b", "parents": [ "dbcb11d7f580544e1733840d6a560715c5cfd9bd" ], "author": { "name": "Isaku Yamahata", "email": "isaku.yamahata@intel.com", "time": "Thu Mar 05 09:47:52 2026 -0800" }, "committer": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Wed May 27 08:37:00 2026 -0700" }, "message": "x86: Replace NOP with CPUID after WRMSR(TSCDEADLINE) to serialize deadline timer\n\nFix apic and vmexit test cases to pass with APIC timer virtualization by\nreplacing the NOP instruction with the CPUID instruction, a serializing\ninstruction. Use CPUID instead of the SERIALIZE instruction for simplicity\nbecause SERIALIZE is not universally available, but CPUID is (on CPUs that\nKVM-Unit-Tests realistically supports).\n\nThe apic and vmexit tests use a WRMSR+NOP sequence to cause the deadline\ntimer to fire immediately at the NOP instruction. Per the SDM[1], WRMSR\nisn\u0027t a serializing instruction when writing TSCDEADLINE, which results in\nfalse failures when APIC timer virtualization is enabled (in the host), as\nthe NOP can be retired before the timer is armed. The test currently\npasses because APIC timer virtualization isn\u0027t yet supported by KVM (in\nwhich case the WRMSR is intercepted and thus is *heavily* serializing), and\npresumably because the test isn\u0027t often run on bare metal.\n\n[1] From SDM 3a Serializing intructions\n An execution of WRMSR to any non-serializing MSR is not\n serializing. Non-serializing MSRs include the following: IA32_SPEC_CTRL\n MSR (MSR index 48H), IA32_PRED_CMD MSR (MSR index 49H), IA32_TSX_CTRL MSR\n (MSR index 122H), IA32_TSC_DEADLINE MSR (MSR index 6E0H), IA32_PKRS MSR\n (MSR index 6E1H), IA32_HWP_REQUEST MSR (MSR index 774H), or any of the\n x2APIC MSRs (MSR indices 802H to 83FH).\n\nSuggested-by: Sean Christopherson \u003cseanjc@google.com\u003e\nSigned-off-by: Isaku Yamahata \u003cisaku.yamahata@intel.com\u003e\nLink: https://patch.msgid.link/f7e98f7d5a21375ad584004db94e0d34806c4840.1772678359.git.isaku.yamahata@intel.com\n[sean: massage changelog]\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "dbcb11d7f580544e1733840d6a560715c5cfd9bd", "tree": "d5a5fae7d96eec12ba12bc302a2823538f57605d", "parents": [ "7586f98f809e942c69c812aa6fa2316f1d063918" ], "author": { "name": "Jim Mattson", "email": "jmattson@google.com", "time": "Fri Feb 27 13:38:34 2026 -0800" }, "committer": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Wed May 27 08:37:00 2026 -0700" }, "message": "x86: nVMX: Add retry loop to advanced RTM debugging subtest\n\nLinux commit 400816f60c54 (\"perf/x86/intel: Implement support for TSX Force\nAbort\") introduced a feature that temporarily disables RTM on Skylake and\nsimilar CPUs (06_55H stepping \u003c\u003d 5, 06_4EH, 06_5EH, 06_8EH stepping \u003c\u003d 0BH,\nand 06_9EH stepping \u003c\u003d 0CH) via the TSX_FORCE_ABORT MSR, so that all four\ngeneral purpose PMCs can be used by perf. This feature is on by default,\nbut can be disabled by writing 0 to /sys/devices/cpu/allow_tsx_force_abort.\n\nWhen TSX_FORCE_ABORT.RTM_FORCE_ABORT[bit 0] is set, all RTM transactions\nwill immediately abort, before the xbegin instruction retires.\n\nThe test of a single-step #DB delivered in a transactional region,\nintroduced in commit 414bd9d5ebd7 (\"x86: nVMX: Basic test of #DB intercept\nin L1\"), does not handle this scenario.\n\nModify the test to identify an immediate RTM transaction abort and to try\nup to 30 times before giving up. If the xbegin instruction never retires,\nreport the test as skipped.\n\nNote that when an RTM transaction aborts, the CPU state is rolled back to\nbefore the xbegin instruction, but the RIP is modified to point to the\nfallback code address. Hence, if the transaction aborts before the\nsingle-step #DB trap is delivered, the first instruction of the fallback\ncode will retire before the single-step #DB trap is delivered.\n\nFixes: 414bd9d5ebd7 (\"x86: nVMX: Basic test of #DB intercept in L1\")\nSigned-off-by: Jim Mattson \u003cjmattson@google.com\u003e\nLink: https://patch.msgid.link/20260227213849.3653331-1-jmattson@google.com\n[sean: add a big comment, use consts instead of #defines]\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "7586f98f809e942c69c812aa6fa2316f1d063918", "tree": "fe017438a85316dfaaf27de2530693bfd83b4abb", "parents": [ "8322ddeda22ba784765e7a5e642029c7932666b6" ], "author": { "name": "Kevin Cheng", "email": "chengkev@google.com", "time": "Wed Dec 24 01:43:24 2025 +0000" }, "committer": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Wed May 27 08:37:00 2026 -0700" }, "message": "x86/svm: Add unsupported instruction intercept test\n\nAdd tests that expect a nested vm exit, due to an unsupported\ninstruction, to be handled by L0 even if L1 intercepts are set for that\ninstruction.\n\nThe new test exercises bug fixed by:\nhttps://lore.kernel.org/all/20251205070630.4013452-1-chengkev@google.com/\n\nSigned-off-by: Kevin Cheng \u003cchengkev@google.com\u003e\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "8322ddeda22ba784765e7a5e642029c7932666b6", "tree": "39bb277478b4c602ee4c6a045c9e0fcabeb1600f", "parents": [ "4d60e2429d63dc0c24990114a8afc89e86c187cc" ], "author": { "name": "Kevin Cheng", "email": "chengkev@google.com", "time": "Wed Dec 24 01:43:23 2025 +0000" }, "committer": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Wed May 27 08:37:00 2026 -0700" }, "message": "x86/svm: Add missing svm intercepts\n\nSome intercepts are missing from the KUT svm testing. Add all missing\nintercepts and reorganize the svm intercept definition/setting/clearing.\n\nSigned-off-by: Kevin Cheng \u003cchengkev@google.com\u003e\nReviewed-by: Yosry Ahmed \u003cyosry.ahmed@linux.dev\u003e\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "05b7715ffd4ae4ef8f0a5dea869f1543d89f936d", "tree": "82e457f2c485c00096eb71f9aec4c50278e4a07a", "parents": [ "02e3b6f161c842e61e3e361a41303a24a2252857" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Mon May 25 08:07:23 2026 -0400" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Tue May 26 09:34:05 2026 +0200" }, "message": "svm_tests: access rflags and rax via this_cpu_guest_regs()\n\nThis is needed now that the VMCB save area is properly updated.\n\nReported-by: Aithal, Srikanth \u003csraithal@amd.com\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260525120723.8265-1-pbonzini@redhat.com\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "02e3b6f161c842e61e3e361a41303a24a2252857", "tree": "38197838b68ef85d27aad99c5bbb56035da40d1c", "parents": [ "15bb3deced752a08bf2d6d06398d6fd0bf2cb484", "ab3bd5f31da41b5370206e2e9c2297547a8da048" ], "author": { "name": "Paolo Bonzini", "email": "bonzini@gnu.org", "time": "Thu May 21 10:53:06 2026 +0000" }, "committer": { "name": "Paolo Bonzini", "email": "bonzini@gnu.org", "time": "Thu May 21 10:53:06 2026 +0000" }, "message": "Merge branch \u0027kvm-x86-manual-cherry-pick\u0027 into \u0027master\u0027\n\nMerge more patches from https://github.com/kvm-x86/kvm-unit-tests\n\nSee merge request kvm-unit-tests/kvm-unit-tests!85" }, { "commit": "ab3bd5f31da41b5370206e2e9c2297547a8da048", "tree": "38197838b68ef85d27aad99c5bbb56035da40d1c", "parents": [ "781db7e4a383bcdba37495bba2983dc58ec6b024" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:45:41 2026 +0200" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:45:56 2026 +0200" }, "message": "x86/vmx: add note that CR2 is not context switched\n\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "781db7e4a383bcdba37495bba2983dc58ec6b024", "tree": "d7ef8fa1087e30f8cb4fccd751189b1733cd3d2a", "parents": [ "6d27a4bfa00c6a4f07d6a2aa8dff53e41537e94d" ], "author": { "name": "Maxim Levitsky", "email": "mlevitsk@redhat.com", "time": "Mon Dec 08 18:39:10 2025 -0500" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:45:56 2026 +0200" }, "message": "Skip PMU portion of vmware_backdoors test if PMU is not enabled.\n\nSince 2019, KVM has an explicit check that if guest\u0027s PMC is disabled,\nthen VMware backdoor via RDPCM is disabled as well.\n\n commit 672ff6cff80ca43bf3258410d2b887036969df5f\n Author: Liran Alon \u003cliran.alon@oracle.com\u003e\n Date: Mon Mar 25 21:10:17 2019 +0200\n KVM: x86: Raise #GP when guest vCPU do not support PMU\n\nFix the test failure by checking if PMU is enabled first.\n\nSigned-off-by: Maxim Levitsky \u003cmlevitsk@redhat.com\u003e\nLink: https://patch.msgid.link/20251208233910.1000465-1-mlevitsk@redhat.com\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "6d27a4bfa00c6a4f07d6a2aa8dff53e41537e94d", "tree": "15467e179d42879fb9bf77a4c6d586895cc2c944", "parents": [ "6da817d6059dd5b1846a9ea37f6940b904f5473d" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Wed Nov 26 11:17:36 2025 -0800" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:45:56 2026 +0200" }, "message": "x86/debug: Fix macro definitions for DR7 local/global enable bits\n\nFix the shifts for the DR7 local/global enable bits. As called out by the\ncomment, the local/global enable bits have a stride of 2, i.e. use every\nother bit.\n\nUse DR2 instead of DR0 in the debug test to create a data breakpoint to\ndemonstrate that using something other than DR0 actually works.\n\nFixes: f1dcfd54 (\"x86: Overhaul definitions for DR6 and DR7 bits\")\nLink: https://patch.msgid.link/20251126191736.907963-1-seanjc@google.com\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "6da817d6059dd5b1846a9ea37f6940b904f5473d", "tree": "92d06ce3f067741537b3c44a87fd2fd5480745d0", "parents": [ "b39288775c40c8861f8872827cc069af9d18dbcd" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu Dec 18 15:26:18 2025 -0800" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:45:56 2026 +0200" }, "message": "x86/cstart: Delete \"local\" version of save_id() to fix x2APIC SMP bug\n\nDelete cstart.S\u0027s version of save_id() to play nice with 32-bit SMP tests\non CPUs that support x2APIC. The local version assumes xAPIC mode and so\ndepending on the underlying \"hardware\" (e.g. AVIC vs. APICv vs. emulated,\nand with or without KVM_X86_QUIRK_LAPIC_MMIO_HOLE), may mark the wrong CPU\nas being online.\n\nFixes: 0991c0ea (\"x86: fix APs with APIC ID more that 255 not showing in id_map\")\nCc: Igor Mammedov \u003cimammedo@redhat.com\u003e\nCc: Peter Xu \u003cpeterx@redhat.com\u003e\nAcked-by: Igor Mammedov \u003cimammedo@redhat.com\u003e\nLink: https://patch.msgid.link/20251218232618.2504147-1-seanjc@google.com\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "b39288775c40c8861f8872827cc069af9d18dbcd", "tree": "a3cb98e867bc8687bbc15b778441b6888a7aed21", "parents": [ "15bb3deced752a08bf2d6d06398d6fd0bf2cb484" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Tue Dec 30 11:13:42 2025 -0800" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:45:56 2026 +0200" }, "message": "x86/svm: Track and handle exit code as an unsigned 64-bit value\n\nTrack and handle SVM\u0027s exit_code as an unsigned 64-bit value. Per the\nAPM, offset 0x70 is a single 64-bit value:\n\n 070h 63:0 EXITCODE\n\nAnd a sane reading of the error values defined in \"Table C-1. SVM Intercept\nCodes\" is that negative values use the full 64 bits:\n\n –1 VMEXIT_INVALID Invalid guest state in VMCB.\n –2 VMEXIT_BUSYBUSY bit was set in the VMSA\n –3 VMEXIT_IDLE_REQUIREDThe sibling thread is not in an idle state\n -4 VMEXIT_INVALID_PMC Invalid PMC state\n\nAnd that interpretation is confirmed by testing on Milan and Turin (by\nsetting bits in CR0[63:32] to generate VMEXIT_INVALID on VMRUN).\n\nFurthermore, Xen has treated exitcode as a 64-bit value since HVM support\nwas adding in 2006 (see Xen commit d1bd157fbc (\"Big merge the HVM\nfull-virtualisation abstractions.\")).\n\nNote, the SVM tests will fail when on KVM builds without commit\nf402ecd7a8b6 (\"KVM: nSVM: Set exit_code_hi to -1 when synthesizing\nSVM_EXIT_ERR (failed VMRUN)\").\n\nLink: https://lore.kernel.org/all/20251113225621.1688428-1-seanjc@google.com\nReviewed-by: Yosry Ahmed \u003cyosry.ahmed@linux.dev\u003e\nLink: https://patch.msgid.link/20251230191342.4052363-1-seanjc@google.com\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "15bb3deced752a08bf2d6d06398d6fd0bf2cb484", "tree": "942643195bccb324eeea3d0661a685504d26f909", "parents": [ "cd84298d3fd02a1d8be38596907980ffab6c526a", "8d37abbf7d6420a299ef8f440405d3a2322c8569" ], "author": { "name": "Paolo Bonzini", "email": "bonzini@gnu.org", "time": "Thu May 21 10:27:19 2026 +0000" }, "committer": { "name": "Paolo Bonzini", "email": "bonzini@gnu.org", "time": "Thu May 21 10:27:19 2026 +0000" }, "message": "Merge branch \u0027vmx-svm-regs-fixes\u0027 into \u0027master\u0027\n\nMerge regs improvements for VMX/SVM tests\n\nSee merge request kvm-unit-tests/kvm-unit-tests!84" }, { "commit": "8d37abbf7d6420a299ef8f440405d3a2322c8569", "tree": "942643195bccb324eeea3d0661a685504d26f909", "parents": [ "92125384eba43bb1a24fd3dd5e33452d6dcf71ea" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 10:59:33 2026 +0200" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:12:19 2026 +0200" }, "message": "svm: fix rflags and rax offsets\n\nThey need to include the offset from the VMCB base to the VMSA, which\nis 0x400.\n\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "92125384eba43bb1a24fd3dd5e33452d6dcf71ea", "tree": "9212d593fa430389a846563526f3ead455c9da0f", "parents": [ "2db07d6f6b0cee0d2c40ad53a2cfaef2017609f6" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:58 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:12:19 2026 +0200" }, "message": "x86/vmx: Write to KVM\u0027s WALL_CLOCK MSR via VM-Entry load list sync in SIPI test\n\nIn the VMX Wait-for-SIPI \u003d\u003e SIPI VM-Exit test, signal that the AP has\nentered the guest by writing to MSR_KVM_WALL_CLOCK_NEW (when supported)\nvia the VM-Entry MSR load list instead of writing to memory from the AP\n_before_ actually doing VM-Enter. Abusing the MSR load list ensures that\nthe AP\u0027s \"ready\" signal to the BSP happens atomically with respect to\nVM-Enter, and thus fixes a race where the BSP can see \"ready\" and send the\nSIPI before the AP has executed VM-Enter. E.g. with a delay inserted on\nthe AP, and no delay on the BSP, the test will hang 100% of the time.\n\nUse MSR_KVM_WALL_CLOCK_NEW as it is pretty much the only MSR that KVM\nemulates as a per-VM MSR, and that has a high likelihood of being\navailable.\n\nKeep the BSP\u0027s delay before send the SIPI so that the test continues to\nwork if MSR_KVM_WALL_CLOCK_NEW isn\u0027t available, e.g. in bare metal (and\nmost KVM) setups, hitting the race is practically impossible.\n\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-19-seanjc@google.com\u003e\n" }, { "commit": "2db07d6f6b0cee0d2c40ad53a2cfaef2017609f6", "tree": "9dbbe2d8b13ed03ea2aa6ce6481dc4f9c850c405", "parents": [ "0833ea0f3410eee7e677b509983046b2a9d9bf5d" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:57 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:12:19 2026 +0200" }, "message": "x86/smp: Align the stack to a 16-byte boundary when invoking SMP function calls\n\nAlign RSP to a 16-byte boundary in the IPI handler for SMP function calls\nbefore calling into C code, as required by the x86-64 ABI. Failure to\nensure the stack is properly aligned leads to obscure failures if a struct\n(or any other object) tagged with __attribute__((aligned(16))) (or any\nalignment greater than 16) is place on the stack. E.g. VM-Enter will fail\non VMX if a vmx_msr_entry structure is placed on the stack.\n\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-18-seanjc@google.com\u003e\n" }, { "commit": "0833ea0f3410eee7e677b509983046b2a9d9bf5d", "tree": "99c40ff8e277f59ca7641a84ec753279f703d4d3", "parents": [ "36f51869080805a5786313c2bf0662fe272fa651" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:56 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:12:19 2026 +0200" }, "message": "x86/vmx: Tag \"struct vmx_msr_entry\" as needing to be 16-byte aligned\n\nMark \"struct vmx_msr_entry\" as 16-byte aligned so that it can be used in\nstatic definitions without generating random VM-Entry failures due to an\nunaligned MSR load/store list.\n\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-17-seanjc@google.com\u003e\n" }, { "commit": "36f51869080805a5786313c2bf0662fe272fa651", "tree": "53fe7f9b131223c18f2acaec599bfffe06127d66", "parents": [ "f94ee0ba4a050d281abf7a2eed31b0bccc323eec" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:55 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:12:19 2026 +0200" }, "message": "x86/kvmclock: Skip kvmclock test when not running on KVM with CLOCKSOURCE2\n\nSkip the kvmclock test if the (virtual) CPU isn\u0027t running on KVM and/or\ndoesn\u0027t have CLOCKSOURCE2. Presumably non-KVM environments simply don\u0027t\nrun the test, but checking for kvmclock support is easy enough. E.g. with\n\n -cpu host,-kvmclock,kvm-pv-enforce-cpuid\n\nthe test will die on WRMSR #GPs without the checks, but generate\n\n SKIP: CPU not running on KVM with CLOCKSOURCE2\n SUMMARY: 1 tests, 1 skipped\n\nwith the appropriate checks.\n\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-16-seanjc@google.com\u003e\n" }, { "commit": "f94ee0ba4a050d281abf7a2eed31b0bccc323eec", "tree": "c43d46b09b275fde9f1d6363123ed02f3d44e7a6", "parents": [ "1231be071c203c9292006eb3cd59c47fed87d3bc" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:54 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:12:19 2026 +0200" }, "message": "x86/kvmclock: Replace spaces with tabs\n\nReplace (8) spaces with tabs in the kvmclock code so that upcoming changes\ndon\u0027t propagate the antiquated formatting.\n\nNo functional change intended.\n\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-15-seanjc@google.com\u003e\n" }, { "commit": "1231be071c203c9292006eb3cd59c47fed87d3bc", "tree": "2760a75132a5f34bd8d344d22499fed754f7b566", "parents": [ "55c87a2054a813c4f514c58624b6c80718a3bc91" ], "author": { "name": "Mathias Krause", "email": "minipli@grsecurity.net", "time": "Thu May 14 14:04:53 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:12:19 2026 +0200" }, "message": "x86/vmx: Initialize test stage in SIPI test *before* launching AP thread\n\nInitialize the VMX test stage in the SIPI test *before* spawning the AP\nthread, as setting the stage after waking the AP can result in the BSP\u0027s\nwrite of \u00270\u0027 clobbering the AP\u0027s write of \u00271\u0027, ultimately causing the test\nto hang because the BSP thinks the AP hasn\u0027t yet entered guest mode.\n\nSigned-off-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\n[sean: write changelog]\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-14-seanjc@google.com\u003e\n" }, { "commit": "55c87a2054a813c4f514c58624b6c80718a3bc91", "tree": "c9c7560397b3b62bdf94bb807d9aed5d5bd1f4dc", "parents": [ "1e39fc4377bd5978c989c79200aa13524a4d55df" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:52 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:12:19 2026 +0200" }, "message": "x86/vmx: Communicate hypercalls via RAX, not a global field\n\nCommunicate hypercall requests via RAX instead of a global field. To\navoid false positives, use a larger magic value that is extremely unlikely\nto be resident in RAX at the time of VMCALL (avoiding false positives is\nis presumably why a global variable was used).\n\nUsing RAX instead of a shared variable ensures multi-vCPU tests won\u0027t\nclobber each other\u0027s hypercalls (no such tests currently exist).\n\nUse the \"abracadabra\" magic number first introduced by KVM selftests,\nbecause if a dad joke is funny one time, it\u0027s funny every time.\n\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-13-seanjc@google.com\u003e\n" }, { "commit": "1e39fc4377bd5978c989c79200aa13524a4d55df", "tree": "b94383c588f739e5e37863b643b756bb74924348", "parents": [ "fdc3b93d22b75fa502ef627426ba8559099fa9c1" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:51 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:12:19 2026 +0200" }, "message": "x86/vmx: Track \"is this CPU in guest mode\" per-CPU\n\nTrack whether or not a CPU is in a SVM/VMX guest on a per-CPU basis to\nplay nice with SVM/VMX tests that run multiple vCPUs. How the VMX tests\nin particular managed to survive this long with shared state is nothing\nshort of amazing.\n\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-12-seanjc@google.com\u003e\n" }, { "commit": "fdc3b93d22b75fa502ef627426ba8559099fa9c1", "tree": "c5a1052cb4175db0a719a2c2fca5c2f046423e2a", "parents": [ "409e86a1e3b051b1b34f8f4192240ab3df88e4a3" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:50 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:12:19 2026 +0200" }, "message": "x86/vmx: Track VMCS \"launched\" state per-CPU\n\nTrack whether or not a VMCS has been \"launched\" per-CPU to play nice with\nVMX tests that use multiple VMCSes. Arguably, it would be better to add a\nstructure to track the current VMCS and its launched state, but there\u0027s no\nimmediate benefit to doing so, and practically speaking the only thing that\nwould be tracked (without support for e.g. eVMCS) would be the \"launched\"\nstate.\n\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-11-seanjc@google.com\u003e\n" }, { "commit": "409e86a1e3b051b1b34f8f4192240ab3df88e4a3", "tree": "8a390ffa709b92215a4450ecd924b05509c52378", "parents": [ "67913cf5d0b00b1a41d0781d34941ab1f4069b10" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:49 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:12:19 2026 +0200" }, "message": "x86/vmx: Swap GPRs after checking \"launched\" status\n\nWhen context switching GPRs before VM-Enter, check if the VMCS has been\nlaunched before loading guest GPRs to ensure the assembly sequence doesn\u0027t\nconsume a guest GPR. The code currently works because \"launched\" is a\nglobal variable and can be read with RIP-relative addressing, but that\nwon\u0027t hold true when launched is tracked per-CPU (or per-VMCS).\n\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-10-seanjc@google.com\u003e\n" }, { "commit": "67913cf5d0b00b1a41d0781d34941ab1f4069b10", "tree": "836b974c8d16cffaab24dc391b601fe712b91db8", "parents": [ "bfcf97436a2156bd4807fc58ed5e9790a4a85e53" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:48 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:12:19 2026 +0200" }, "message": "x86/vmx: Use separate VMCSes for BSP vs. AP in INIT test\n\nAllocate and use a separate VMCS for the AP CPU in VMX\u0027s INIT test, and\nsimply mark the guest as finished on the BSP. Sharing a VMCS between CPUs\nrequires _more_ code than allocating a dedicated VMCS, and completely\nfalls apart if things like \"launched\" are made per-CPU (spoiler alert).\n\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-9-seanjc@google.com\u003e\n" }, { "commit": "bfcf97436a2156bd4807fc58ed5e9790a4a85e53", "tree": "5269e46bb9ec20efaf3e492ea66b3f87544a7c87", "parents": [ "bbad9ba64b60066d3352d9736f7bb9ae4afc9fd6" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:47 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:12:19 2026 +0200" }, "message": "x86/svm: Don\u0027t VMLOAD/VMSAVE \"guest\" state around VMRUN\n\nDrop the completely asinine and *extremely* confusing VMLOAD and VMSAVE\nusage around VMRUN, as loading and saving _just_ guest state is both\nunnecessary and dangerous. E.g. GS.base, which KUT uses for per-CPU data,\nis handled by VMLOAD/VMSAVE, and so loading guest state before VMRUN\nwithout loading host state after #VMEXIT is wildly broken. The only\nreason the code \"works\" is because all relevant host state is copied\nverbatim into the guest\u0027s save area, i.e. the host and guest use the same\nstate. Double-down on sharing state between host and guest as a proper\nfix is much more involved and delicate, e.g. would require ensuring\nGS.base is loaded with the host\u0027s value prior to swapping GPRs (which are\nper-CPU).\n\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-8-seanjc@google.com\u003e\n" }, { "commit": "bbad9ba64b60066d3352d9736f7bb9ae4afc9fd6", "tree": "fc5b95fe528f5efef47a2ffc6291eb1066914671", "parents": [ "c7197bfe2bad1c969c64893848e890bf627b5e76" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:46 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 12:12:07 2026 +0200" }, "message": "x86/virt: Track \"guest regs\" using per-CPU variable\n\nMake the guest_regs structure used to context switch registers between\nhost and guest per-CPU to fix a bug where VMX tests that run multiple\nvCPUs can fail due to register corruption, e.g. two CPUs enter the guest\nin quick succession, only one of the CPU\u0027s registers will be preserved\nacross VM-Enter \u003d\u003e VM-Exit.\n\nReported-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nCloses: https://lore.kernel.org/all/3bac29b9-4c49-4e5d-997e-9e4019a2fceb@grsecurity.net\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-7-seanjc@google.com\u003e\n" }, { "commit": "c7197bfe2bad1c969c64893848e890bf627b5e76", "tree": "6a5a3d63a8cbcdec99ccb94adbf84e57a4b7742d", "parents": [ "73e6d71c54ff22e4a88e92931b8a8338e0739542" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:45 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 11:05:25 2026 +0200" }, "message": "x86/virt: Use macro shenanigans to get reg offsets when swapping guest/host regs\n\nReplace the hand-coded literal offsets in the guest/host assembly code\nwith programmatically generated offsets to make the code more readable and\neasier to maintain. E.g. this will make it much, much easier to make\nthe guest register structure per-CPU.\n\nTo workaround offsetof() being resolved at compile-time, i.e. not by the\npreprocessor, provide a macro to define the immediate constraints for\ninline assembly.\n\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-6-seanjc@google.com\u003e\n" }, { "commit": "73e6d71c54ff22e4a88e92931b8a8338e0739542", "tree": "29bb442c2324d766c8e2f1481a4b57a4f9db5477", "parents": [ "5fb9bcc85c1367c039bc3ae4137f00fd2ede2949" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:44 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 11:05:24 2026 +0200" }, "message": "x86: Dedup guest/host context switch of registers across SVM and VMX\n\nDeduplicate the context switching of registers across VM-Enter\u003c\u003d\u003eVM-Exit\nbetween SVM and VMX. The required functionality and implementations are\npractically identical, literally the only difference is that SVM doesn\u0027t\nneed (or want) to manually swap RAX as SVM automatically swaps RAX at\nVMRUN and #VMEXIT.\n\nOpportunistically rename the structure to \"guest_regs\" to clarify its\npurpose, and to avoid conflicts, e.g. with realmode\u0027s \"struct regs\".\n\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-5-seanjc@google.com\u003e\n" }, { "commit": "5fb9bcc85c1367c039bc3ae4137f00fd2ede2949", "tree": "2432498a72244ad1f332188c9c8d633c4c0eced3", "parents": [ "2a00b01d7b2fc2cc9c292d965a7a08429d9624ed" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:43 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 10:20:31 2026 +0200" }, "message": "x86/svm: Sort (and swap) GPRs by their index, not alphabetically\n\nSort all GPRs in the nested SVM infrastructure by their index, not\nalphabetically. This will allow sharing code between SVM and VMX for\ncontext switching GPRs between guest and host.\n\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-4-seanjc@google.com\u003e\n" }, { "commit": "2a00b01d7b2fc2cc9c292d965a7a08429d9624ed", "tree": "b308a3e563f092e81884e865c77093ce89314911", "parents": [ "f9a8f5ab43ef5aa7cf8d6ae55377ea8c967b999d" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:42 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 10:20:31 2026 +0200" }, "message": "x86/vmx: Drop unused guest_regs \"support\" in nested VMX infrastructure\n\nDrop vmx_tests.guest_regs as no tests use the functionality, the field is\nvery misleading (it\u0027s only used to set the initial regs, i.e. it\u0027s not an\nup-to-date snapshot), and per-test register state doesn\u0027t play nice with\ntests that create and run multiple vCPUs.\n\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-3-seanjc@google.com\u003e\n" }, { "commit": "f9a8f5ab43ef5aa7cf8d6ae55377ea8c967b999d", "tree": "bba9f5d4a3940e29e22f0d936c0114fcab7c0bb6", "parents": [ "cd84298d3fd02a1d8be38596907980ffab6c526a" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 14:04:41 2026 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu May 21 10:20:31 2026 +0200" }, "message": "x86/vmx: Drop unused SYSENTER \"support\" in nested VMX infrastructure\n\nDrop the unused SYSTENTER \"support\" from the nested VMX infrastructure, in\nquotes because the code is half-baked (and that\u0027s being generous) and\nlikely has never been used.\n\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\nTested-by: Mathias Krause \u003cminipli@grsecurity.net\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260514210500.1626871-2-seanjc@google.com\u003e\n" }, { "commit": "cd84298d3fd02a1d8be38596907980ffab6c526a", "tree": "010507b1da603b03f19375b1172352ebd991de5e", "parents": [ "11a4d95cf1b57aa890de6f8cce97d1ec470a3c08" ], "author": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Wed May 20 10:40:52 2026 +0200" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Wed May 20 11:00:55 2026 +0200" }, "message": "x86: Work-around failing intel-iommu test due to bug in GCC v16.1\n\nGCC v16.1 has a bug that causes the intel-iommu test to fail:\n\n https://gcc.gnu.org/bugzilla/show_bug.cgi?id\u003d125180\n\nAdd a work-around for the time being until this is fixed, so we can\nget our CI green again.\n\nMessage-ID: \u003c20260520084546.365816-1-thuth@redhat.com\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "11a4d95cf1b57aa890de6f8cce97d1ec470a3c08", "tree": "9f440d804bb0a3d45a5b43bfacb05dd7a8cc0d53", "parents": [ "b740fab218f1ee344fe92cd876f5ae4201ee8d8f" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Wed May 20 10:37:32 2026 +0200" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Wed May 20 11:00:14 2026 +0200" }, "message": "build: add -Wno-override-init\n\nThe -Woverride-init flag (also known as -Winitializer-overrides in clang,\nbut it supports both spellings) warns about code that may be intentional\nor not. While the unintentional ones tend to be real bugs, overall the\nidea of overriding function pointers is more useful than the warning.\n\nFixes: f4c5838c (\"svm: add basic GMET tests\", 2026-05-12)\nReported-by: Thomas Huth \u003cthuth@redhat.com\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20260520083732.360181-1-pbonzini@redhat.com\u003e\nTested-by: Thomas Huth \u003cthuth@redhat.com\u003e\n[thuth: fix commit message]\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "b740fab218f1ee344fe92cd876f5ae4201ee8d8f", "tree": "2cba3e0e50fbfe078dfe9e83c7dcc310f0244dae", "parents": [ "9eb6c57313060d34f7e5b2ac6f90bb5873bbe2ff" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Wed May 06 15:06:42 2026 +0200" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Wed May 20 10:24:02 2026 +0200" }, "message": "realmode: load above stack\n\nThe bottom 32K of memory are generally reserved for use by the BIOS;\nfor example, traditionally the boot loader is placed at 0x7C00 and\nthe stack grows below that address.\n\nIt turns out that with some versions of clang, realmode.flat has\nbecome big enough that it overlaps the stack used by the multiboot\noption ROM loader. The result is that a couple instructions are\noverwritten. Typically one or two tests fail and that\u0027s it...\n\nMove the code above the forbidden region, in real 90s style.\n\nAdditionally, we\u0027ve got to compile the test with -Os now, otherwise\nthe code might get too big when compiling with older versions of clang\n(e.g. Clang v20), so linking fails with:\n\n x86/realmode.o: In function `realmode_start\u0027:\n realmode.c:(.text+0x79): relocation truncated to fit: R_386_16 against `.bss\u0027\n realmode.c:(.text+0x82): relocation truncated to fit: R_386_16 against `.bss\u0027\n realmode.c:(.text+0x8b): relocation truncated to fit: R_386_16 against `.bss\u0027\n realmode.c:(.text+0x94): relocation truncated to fit: R_386_16 against `.bss\u0027\n\nUnfortunately, the -Os triggers compiler warnings in this code\nwith GCC v16:\n\n In function ‘test_int’,\n inlined from ‘realmode_start’ at x86/realmode.c:1781:2:\n x86/realmode.c:828:28: error: array subscript 0 is outside array bounds\n of ‘u32[0]’ {aka ‘unsigned int[]’} [-Werror\u003darray-bounds\u003d]\n 828 | *(u32 *)(0x11 * 4) \u003d 0x1000; /* Store a pointer to address 0x1000 in IDT entry 0x11 */\n | ~~~~~~~~~~~~~~~~~~~^~~~~~~~\n In function ‘realmode_start’:\n cc1: note: source object is likely at address zero\n In function ‘test_sti_inhibit’,\n inlined from ‘realmode_start’ at x86/realmode.c:1782:2:\n x86/realmode.c:841:28: error: array subscript 0 is outside array bounds\n of ‘u32[0]’ {aka ‘unsigned int[]’} [-Werror\u003darray-bounds\u003d]\n 841 | *(u32 *)(0x73 * 4) \u003d 0x1000; /* Store IRQ 11 handler in the IDT */\n | ~~~~~~~~~~~~~~~~~~~^~~~~~~~\n In function ‘realmode_start’:\n cc1: note: source object is likely at address zero\n cc1: all warnings being treated as errors\n\n... so additionally we also have to compile this test with this warning\ndisabled now.\n\nReported-by: Thomas Huth \u003cthuth@redhat.com\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\nMessage-ID: \u003c20240604143507.1041901-1-pbonzini@redhat.com\u003e\n[thuth: Add -Os and -Wno-array-bounds to CFLAGS to avoid other problems]\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\nMessage-ID: \u003c20260506130642.2571332-1-thuth@redhat.com\u003e\n" }, { "commit": "4d60e2429d63dc0c24990114a8afc89e86c187cc", "tree": "db5eadabcf7a4e3063a562dea87cb314e5579161", "parents": [ "bf60564d199465b7bf8758cc8f904d2860e93a18" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Tue Dec 30 11:13:42 2025 -0800" }, "committer": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 10:27:27 2026 -0700" }, "message": "x86/svm: Track and handle exit code as an unsigned 64-bit value\n\nTrack and handle SVM\u0027s exit_code as an unsigned 64-bit value. Per the\nAPM, offset 0x70 is a single 64-bit value:\n\n 070h 63:0 EXITCODE\n\nAnd a sane reading of the error values defined in \"Table C-1. SVM Intercept\nCodes\" is that negative values use the full 64 bits:\n\n –1 VMEXIT_INVALID Invalid guest state in VMCB.\n –2 VMEXIT_BUSYBUSY bit was set in the VMSA\n –3 VMEXIT_IDLE_REQUIREDThe sibling thread is not in an idle state\n -4 VMEXIT_INVALID_PMC Invalid PMC state\n\nAnd that interpretation is confirmed by testing on Milan and Turin (by\nsetting bits in CR0[63:32] to generate VMEXIT_INVALID on VMRUN).\n\nFurthermore, Xen has treated exitcode as a 64-bit value since HVM support\nwas adding in 2006 (see Xen commit d1bd157fbc (\"Big merge the HVM\nfull-virtualisation abstractions.\")).\n\nNote, the SVM tests will fail when on KVM builds without commit\nf402ecd7a8b6 (\"KVM: nSVM: Set exit_code_hi to -1 when synthesizing\nSVM_EXIT_ERR (failed VMRUN)\").\n\nLink: https://lore.kernel.org/all/20251113225621.1688428-1-seanjc@google.com\nReviewed-by: Yosry Ahmed \u003cyosry.ahmed@linux.dev\u003e\nLink: https://patch.msgid.link/20251230191342.4052363-1-seanjc@google.com\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "bf60564d199465b7bf8758cc8f904d2860e93a18", "tree": "3be87e9fc98acfd0c8a1a5d338cf06ab3ba3025c", "parents": [ "e1a0812dc2b571241c63a60c0f4714f360205408" ], "author": { "name": "Maxim Levitsky", "email": "mlevitsk@redhat.com", "time": "Mon Dec 08 18:39:10 2025 -0500" }, "committer": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 10:27:27 2026 -0700" }, "message": "Skip PMU portion of vmware_backdoors test if PMU is not enabled.\n\nSince 2019, KVM has an explicit check that if guest\u0027s PMC is disabled,\nthen VMware backdoor via RDPCM is disabled as well.\n\n commit 672ff6cff80ca43bf3258410d2b887036969df5f\n Author: Liran Alon \u003cliran.alon@oracle.com\u003e\n Date: Mon Mar 25 21:10:17 2019 +0200\n KVM: x86: Raise #GP when guest vCPU do not support PMU\n\nFix the test failure by checking if PMU is enabled first.\n\nSigned-off-by: Maxim Levitsky \u003cmlevitsk@redhat.com\u003e\nLink: https://patch.msgid.link/20251208233910.1000465-1-mlevitsk@redhat.com\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "e1a0812dc2b571241c63a60c0f4714f360205408", "tree": "a57988e2dd51a95e54d6d70271008a4a157a0e97", "parents": [ "d0052ffe48dadd7a5abea35f7a26c6ee85184d5e" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Wed Nov 26 11:17:36 2025 -0800" }, "committer": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 10:27:26 2026 -0700" }, "message": "x86/debug: Fix macro definitions for DR7 local/global enable bits\n\nFix the shifts for the DR7 local/global enable bits. As called out by the\ncomment, the local/global enable bits have a stride of 2, i.e. use every\nother bit.\n\nUse DR2 instead of DR0 in the debug test to create a data breakpoint to\ndemonstrate that using something other than DR0 actually works.\n\nFixes: f1dcfd54 (\"x86: Overhaul definitions for DR6 and DR7 bits\")\nLink: https://patch.msgid.link/20251126191736.907963-1-seanjc@google.com\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "d0052ffe48dadd7a5abea35f7a26c6ee85184d5e", "tree": "7fd91e5478a69b5f18887fe301d7cf41a0157c25", "parents": [ "9eb6c57313060d34f7e5b2ac6f90bb5873bbe2ff" ], "author": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu Dec 18 15:26:18 2025 -0800" }, "committer": { "name": "Sean Christopherson", "email": "seanjc@google.com", "time": "Thu May 14 10:17:29 2026 -0700" }, "message": "x86/cstart: Delete \"local\" version of save_id() to fix x2APIC SMP bug\n\nDelete cstart.S\u0027s version of save_id() to play nice with 32-bit SMP tests\non CPUs that support x2APIC. The local version assumes xAPIC mode and so\ndepending on the underlying \"hardware\" (e.g. AVIC vs. APICv vs. emulated,\nand with or without KVM_X86_QUIRK_LAPIC_MMIO_HOLE), may mark the wrong CPU\nas being online.\n\nFixes: 0991c0ea (\"x86: fix APs with APIC ID more that 255 not showing in id_map\")\nCc: Igor Mammedov \u003cimammedo@redhat.com\u003e\nCc: Peter Xu \u003cpeterx@redhat.com\u003e\nAcked-by: Igor Mammedov \u003cimammedo@redhat.com\u003e\nLink: https://patch.msgid.link/20251218232618.2504147-1-seanjc@google.com\nSigned-off-by: Sean Christopherson \u003cseanjc@google.com\u003e\n" }, { "commit": "9eb6c57313060d34f7e5b2ac6f90bb5873bbe2ff", "tree": "1d6cd0b8dc1af12fc0bc08a9f2c294a079f232fd", "parents": [ "c634d671b1801a97b774e6601a9f6774557541d8", "6a061f5f72fc473e7e6f1512375fd1d3a11b11a0" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Tue May 12 13:03:25 2026 +0200" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Tue May 12 13:03:25 2026 +0200" }, "message": "Merge branch \u0027mbec\u0027 into HEAD\n" }, { "commit": "6a061f5f72fc473e7e6f1512375fd1d3a11b11a0", "tree": "1d6cd0b8dc1af12fc0bc08a9f2c294a079f232fd", "parents": [ "a225b3e47ac5e3c08b41d4c9cff3a5616bfb84b3" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu Mar 26 10:20:24 2026 -0400" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Tue May 12 06:57:21 2026 -0400" }, "message": "x86/vmx: add EPT tests covering XU permission\n\nAdd tests to validate MBEC execute access when XU\u003d1, with and without XS\u003d1.\n\nCo-authored-by: Jon Kohler \u003cjon@nutanix.com\u003e\nSigned-off-by: Jon Kohler \u003cjon@nutanix.com\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "a225b3e47ac5e3c08b41d4c9cff3a5616bfb84b3", "tree": "95b6a3b95b41010db4a648b5d8ffb94184ee95e7", "parents": [ "1266148094666d2140618e8cb6f98f76aa2c8e4f" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu Mar 26 10:20:19 2026 -0400" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Tue May 12 06:57:21 2026 -0400" }, "message": "x86/vmx: run EPT tests with MBEC enabled when available\n\nCheck that the XS bit does not allow execution of user-mode pages\nwhen MBEC is available (and enabled); this requires tweaking\nthe guest page tables to set U\u003d0 for OP_EXEC. Update the unit test\nconfiguration to include a specific test case for MBEC.\n\nCo-authored-by: Jon Kohler \u003cjon@nutanix.com\u003e\nSigned-off-by: Jon Kohler \u003cjon@nutanix.com\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "1266148094666d2140618e8cb6f98f76aa2c8e4f", "tree": "a5aeb9d3d88a70c18103895b7de8a66d3e367882", "parents": [ "88b1f6cf23dfbcefcf8322dc8f39abe4c9e80f29" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu Mar 26 10:20:10 2026 -0400" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Tue May 12 06:57:21 2026 -0400" }, "message": "x86/vmx: add user execution operation to EPT access tests\n\nIntroduce a new ept_access_op, OP_EXEC_USER, to the EPT access tests to\nprepare for MBEC, which allows execution of user-level code.\n\nSince the tests do not support MBEC yet, the expected behavior is the\nsame as for OP_EXEC.\n\nCo-authored-by: Jon Kohler \u003cjon@nutanix.com\u003e\nSigned-off-by: Jon Kohler \u003cjon@nutanix.com\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "88b1f6cf23dfbcefcf8322dc8f39abe4c9e80f29", "tree": "9b46d0d2129c43580f4807ff50054ef1288fcf9d", "parents": [ "780ffa87e75a1ddb3be7f442530c8c27581c8cf0" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu Mar 26 10:19:46 2026 -0400" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Tue May 12 06:57:21 2026 -0400" }, "message": "x86/vmx: add mode-based execute control test for Skylake and above\n\nIntroduce a new test for mode-based execute control (MBEC) in the VMX\ncontrols, validating the dependency between MBEC and EPT VM-execution\ncontrols. The test ensures that VM entry fails when MBEC is enabled\nwithout EPT, and succeeds in valid combinations.\n\nUpdate the unit test configuration to include a specific test case for\nMBEC on Skylake-Server CPU model, as that was the first CPU series to\nhave MBEC.\n\nPassing test result\nTest suite: vmx_controls_test_mbec\nPASS: MBEC disabled, EPT disabled (valid combination): vmlaunch succeeds\nPASS: MBEC enabled, EPT disabled (invalid combination): vmlaunch fails\nPASS: MBEC enabled, EPT disabled (invalid combination): VMX inst error is 7 (actual 7)\nPASS: MBEC enabled, EPT enabled (valid combination): vmlaunch succeeds\nPASS: MBEC disabled, EPT enabled (valid combination): vmlaunch succeeds\n\nTest ran with \"-vmx-mbec\":\nTest suite: vmx_controls_test_mbec\nSKIP: test_mode_based_execute_control : \"Secondary execution\" or\n\"enable EPT\" or \"enable mode-based execute control\" control not supported\n\nCo-authored-by: Jon Kohler \u003cjon@nutanix.com\u003e\nSigned-off-by: Jon Kohler \u003cjon@nutanix.com\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "780ffa87e75a1ddb3be7f442530c8c27581c8cf0", "tree": "f9136e3b88566d26823cb59db636c3ea9371216c", "parents": [ "4d2d44a6d1486a131c3de396a9604f6d518b02ad" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Thu Mar 26 07:54:47 2026 -0400" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Tue May 12 06:57:21 2026 -0400" }, "message": "x86/vmx: diagnose unexpected EPT violations\n\nKnowing the exit qualification when a test incorrectly raises an\nEPT violation greatly simplifies debugging. This requires a tweak to\n__TEST_EQ, allowing any code block instead of just a function name for\nthe abort code.\n\nFor this particular case, include advanced vmexit info in the diagnosis.\n\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "4d2d44a6d1486a131c3de396a9604f6d518b02ad", "tree": "4b2b7c29a31c6de517f498a68cd9f187536e471a", "parents": [ "f4c5838c543e718cf100ba3aab69377cfec6736e" ], "author": { "name": "Jon Kohler", "email": "jon@nutanix.com", "time": "Mon Dec 22 22:48:42 2025 -0700" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Tue May 12 06:57:21 2026 -0400" }, "message": "x86/vmx: update EPT installation to use EPT_PRESENT flag\n\nPrepare for MBEC EPT access test cases by refactoring the EPT\ninstallation logic in vmx_tests.c and vmx.c to replace the use of\nEPT_RA | EPT_WA | EPT_EA flags with the EPT_PRESENT flag; this\nwill allow adding the XU bit to all upper-level page tables\neasily when MBEC is active.\n\nNote that EPT_PRESENT is not used testing the RWX combination\nspecifically.\n\nNo functional change intended.\n\nSigned-off-by: Jon Kohler \u003cjon@nutanix.com\u003e\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "f4c5838c543e718cf100ba3aab69377cfec6736e", "tree": "9cb7edb721fb9ed1b9eafb501b2ad72a1bc61332", "parents": [ "ce81613436eef1405b8b732ca718d95ec0006cbf" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Wed Mar 18 13:46:51 2026 -0400" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Tue May 12 06:57:19 2026 -0400" }, "message": "svm: add basic GMET tests\n\nThese cover three basic scenarios of running successfully,\nfailing due to NX\u003d1 and failing due to U/S\u003d1.\n\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "ce81613436eef1405b8b732ca718d95ec0006cbf", "tree": "a59ef593831b3dac74ec478c4a52c4834b6fc4b7", "parents": [ "534b9e832e66cbcf4c0d92d8ccd9f7fed8ef8536" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Wed Mar 18 13:40:23 2026 -0400" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Tue May 12 06:36:43 2026 -0400" }, "message": "add definitions for nested_ctl\n\nRight now only bit 0 was used, and it was hard coded. Change\nthat to a #define.\n\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "534b9e832e66cbcf4c0d92d8ccd9f7fed8ef8536", "tree": "2f7b9ce4b844913737f06f50005d40793f2d9dcc", "parents": [ "c634d671b1801a97b774e6601a9f6774557541d8" ], "author": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Wed Mar 18 13:36:25 2026 -0400" }, "committer": { "name": "Paolo Bonzini", "email": "pbonzini@redhat.com", "time": "Tue May 12 06:36:43 2026 -0400" }, "message": "move PFERR_* constants to lib\n\nAllow using them from the SVM tests as well.\n\nSigned-off-by: Paolo Bonzini \u003cpbonzini@redhat.com\u003e\n" }, { "commit": "c634d671b1801a97b774e6601a9f6774557541d8", "tree": "d0856ae2eef87cc73ecb3e12184661bde2e07cff", "parents": [ "bdf7bbc503b6d17b43906ca681acd6fe4fe483ba" ], "author": { "name": "Christoph Schlameuss", "email": "schlameuss@linux.ibm.com", "time": "Mon Apr 27 19:36:46 2026 +0200" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon May 04 09:06:09 2026 +0200" }, "message": "b4: Add b4 config with default prefix\n\nb4.send-prefixes adds the prefixes when creating a new patch series.\n\nSigned-off-by: Christoph Schlameuss \u003cschlameuss@linux.ibm.com\u003e\nReviewed-by: Thomas Huth \u003cthuth@redhat.com\u003e\nMessage-ID: \u003c20260427-b4-cmdline-v2-4-0fea2a50a9d0@linux.ibm.com\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "bdf7bbc503b6d17b43906ca681acd6fe4fe483ba", "tree": "d1221f132930a5312a082cf034fb2b9165604bb4", "parents": [ "06b423e878a00a313535634f3e44cfb3c8e15fc8" ], "author": { "name": "Christoph Schlameuss", "email": "schlameuss@linux.ibm.com", "time": "Mon Apr 27 19:36:45 2026 +0200" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon May 04 09:06:09 2026 +0200" }, "message": "scripts/get_maintainer.pl: Ignore --nogit-chief-penguins option\n\nb4 by default calls the get_maintainer.pl script with the\n\u0027--nogit-chief-penguins\u0027 option letting the \u0027b4 prep --auto-to-cc\u0027 fail.\n\nAdding parsing of that option without any related functionality to allow\nsimple usage of b4 in the development workflow.\n\nSigned-off-by: Christoph Schlameuss \u003cschlameuss@linux.ibm.com\u003e\nReviewed-by: Thomas Huth \u003cthuth@redhat.com\u003e\nMessage-ID: \u003c20260427-b4-cmdline-v2-3-0fea2a50a9d0@linux.ibm.com\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "06b423e878a00a313535634f3e44cfb3c8e15fc8", "tree": "c7f00ffccb487bb26f76383980cdc08599c7d4f7", "parents": [ "7b78213f982346bd7a45252e7f8aafc45502a04c" ], "author": { "name": "Christoph Schlameuss", "email": "schlameuss@linux.ibm.com", "time": "Mon Apr 27 19:36:44 2026 +0200" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon May 04 09:06:09 2026 +0200" }, "message": "scripts/checkpatch.pl: Create a project specific codespell config\n\nProvide a codespell config to actually let it do something.\nObviously codespell is not happy about the addition of these misspellings\nhere.\n\nSigned-off-by: Christoph Schlameuss \u003cschlameuss@linux.ibm.com\u003e\nReviewed-by: Thomas Huth \u003cthuth@redhat.com\u003e\nMessage-ID: \u003c20260427-b4-cmdline-v2-2-0fea2a50a9d0@linux.ibm.com\u003e\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "7b78213f982346bd7a45252e7f8aafc45502a04c", "tree": "54a02e8bedb7f015d7ee37450bcb6d12a08ce1d5", "parents": [ "ea91ac1763561b23e7eba3f7c1fa3d45f29b89be" ], "author": { "name": "Christoph Schlameuss", "email": "schlameuss@linux.ibm.com", "time": "Mon Apr 27 19:36:43 2026 +0200" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon May 04 09:05:20 2026 +0200" }, "message": "scripts/checkpatch.pl: Add (almost) empty const_structs configs\n\nWithout these files each patch is flagged with these errors providing no\nvalue and swamping actually found warnings and errors:\n\n● xxxxxxxxxxxx: commit title\n ● checkpatch.pl: No typos will be found - file \u0027.../kvm-unit-tests/scripts/spelling.txt\u0027: No such file or directory\n ● checkpatch.pl: No structs that should be const will be found - file \u0027.../kvm-unit-tests/scripts/const_structs.checkpatch\u0027: No such file or directory\n\nFixes: 846737f068d9 (\"checkpatch support\")\nSigned-off-by: Christoph Schlameuss \u003cschlameuss@linux.ibm.com\u003e\nReviewed-by: Thomas Huth \u003cthuth@redhat.com\u003e\nMessage-ID: \u003c20260427-b4-cmdline-v2-1-0fea2a50a9d0@linux.ibm.com\u003e\n[thuth: Tweaked title of the patch]\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "ea91ac1763561b23e7eba3f7c1fa3d45f29b89be", "tree": "797f7f8b386a6962299d0ea5d4278b87ff8b8e98", "parents": [ "1baa012bed43f8822ee9329d480c4fd5a3285c14" ], "author": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon Apr 13 17:04:44 2026 +0200" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Fri Apr 17 19:54:49 2026 +0200" }, "message": "Update gitlab-CI jobs to Fedora 43\n\nFedora 40 is EOL since a while already, so let\u0027s update to a more\nrecent version of Fedora here now. While we\u0027re at it, also refresh\nthe lists of tests according to what we can run with TCG of the\nlatest version of QEMU.\n\nSomething also has changed in the package dependencies in Fedora 43:\nThe \"ps\" program is not available by default anymore in some of the\njobs, so make sure to install it first via the \"procps-ng\" package now.\n\nAdditionallyly, the *-efi jobs don\u0027t seem to work right with the QEMU\nor EDK2 firmware from Fedora 43 yet, so keep those pinned to an older\nversion for now until somebody tackled that problem.\n\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\nMessage-ID: \u003c20260413150444.28501-1-thuth@redhat.com\u003e\n" }, { "commit": "1baa012bed43f8822ee9329d480c4fd5a3285c14", "tree": "9da0c0b4fa75cd4f9747adac46005365fe0ff667", "parents": [ "6123bbbc271255d61873763b5fb9c4a69acfcfec" ], "author": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Fri Apr 17 19:49:25 2026 +0200" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Fri Apr 17 19:49:25 2026 +0200" }, "message": "MAINTAINERS: Update s390x reviewers\n\nDavid left Red Hat some months ago already, so his e-mail address\nthere is no longer working.\nWith regards to my entry - I am also not directly involved in s390x\nrelated work anymore, so remove my line. The s390x section still has\nthree maintainers, so there should be still enough eyes on s390x\nrelated code anyway.\n\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\n" }, { "commit": "6123bbbc271255d61873763b5fb9c4a69acfcfec", "tree": "4dadab9c66f354975159f1e29b13544cd7e96618", "parents": [ "7e5476207afb6445c29b8a7f463fbe075bdff326" ], "author": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Mon Apr 13 11:49:48 2026 +0200" }, "committer": { "name": "Thomas Huth", "email": "thuth@redhat.com", "time": "Wed Apr 15 18:43:04 2026 +0200" }, "message": "x86/eventinj: Fix flush_cache() macro for the newer versions of Clang\n\nClang v21.1.8 from Fedora 43 complains:\n\n x86/eventinj.c:347:2: error: variable \u0027__l\u0027 is uninitialized when passed\n as a const pointer argument here [-Werror,-Wuninitialized-const-pointer]\n 347 | flush_stack();\n | ^~~~~~~~~~~~~\n x86/eventinj.c:39:33: note: expanded from macro \u0027flush_stack\u0027\n 39 | flush_phys_addr(virt_to_phys(\u0026__l));\n | ^~~\n\nInitialize the temporary variable to 0 to avoid the warning.\n\nSigned-off-by: Thomas Huth \u003cthuth@redhat.com\u003e\nMessage-ID: \u003c20260413094948.14505-1-thuth@redhat.com\u003e\n" } ], "next": "7e5476207afb6445c29b8a7f463fbe075bdff326" }