// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
 * Author: Teresa Remmet <t.remmet@phytec.de>
 */

/dts-v1/;

#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/leds/leds-pca9532.h>
#include <dt-bindings/pwm/pwm.h>
#include "imx8mp-phycore-som.dtsi"

/ {
	model = "PHYTEC phyBOARD-Pollux i.MX8MP";
	compatible = "phytec,imx8mp-phyboard-pollux-rdk",
		     "phytec,imx8mp-phycore-som", "fsl,imx8mp";

	chosen {
		stdout-path = &uart1;
	};

	backlight_lvds: backlight {
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_lvds1>;
		brightness-levels = <0 4 8 16 32 64 128 255>;
		default-brightness-level = <11>;
		enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
		num-interpolated-steps = <2>;
		power-supply = <&reg_lvds1_reg_en>;
		pwms = <&pwm3 0 50000 0>;
	};

	panel1_lvds: panel-lvds {
		compatible = "edt,etml1010g3dra";
		backlight = <&backlight_lvds>;
		power-supply = <&reg_vcc_3v3_sw>;

		port {
			panel1_in: endpoint {
				remote-endpoint = <&ldb_lvds_ch1>;
			};
		};
	};

	reg_vcc_5v_sw: regulator-vcc-5v-sw {
		compatible = "regulator-fixed";
		regulator-always-on;
		regulator-boot-on;
		regulator-max-microvolt = <5000000>;
		regulator-min-microvolt = <5000000>;
		regulator-name = "VCC_5V_SW";
	};

	reg_can1_stby: regulator-can1-stby {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_flexcan1_reg>;
		gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "can1-stby";
	};

	reg_can2_stby: regulator-can2-stby {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_flexcan2_reg>;
		gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
		regulator-max-microvolt = <3300000>;
		regulator-min-microvolt = <3300000>;
		regulator-name = "can2-stby";
	};

	reg_lvds1_reg_en: regulator-lvds1 {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
		regulator-max-microvolt = <1200000>;
		regulator-min-microvolt = <1200000>;
		regulator-name = "lvds1_reg_en";
	};

	reg_usb1_vbus: regulator-usb1-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb1_vbus>;
		gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
		regulator-max-microvolt = <5000000>;
		regulator-min-microvolt = <5000000>;
		regulator-name = "usb1_host_vbus";
	};

	reg_usdhc2_vmmc: regulator-usdhc2 {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
		regulator-name = "VSD_3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		startup-delay-us = <100>;
		off-on-delay-us = <12000>;
	};

	reg_vcc_3v3_sw: regulator-vcc-3v3-sw {
		compatible = "regulator-fixed";
		regulator-name = "VCC_3V3_SW";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};
};

/* TPM */
&ecspi1 {
	#address-cells = <1>;
	#size-cells = <0>;
	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	status = "okay";

	tpm: tpm@0 {
		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
		reg = <0>;
		spi-max-frequency = <38000000>;
	};
};

&eqos {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_eqos>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	status = "okay";

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0x1>;
			ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
			ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
			enet-phy-lane-no-swap;
		};
	};
};

/* CAN FD */
&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	xceiver-supply = <&reg_can1_stby>;
	status = "okay";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	xceiver-supply = <&reg_can2_stby>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default", "gpio";
	pinctrl-0 = <&pinctrl_i2c2>;
	pinctrl-1 = <&pinctrl_i2c2_gpio>;
	sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
	status = "okay";

	eeprom@51 {
		compatible = "atmel,24c02";
		reg = <0x51>;
		pagesize = <16>;
		vcc-supply = <&reg_vcc_3v3_sw>;
	};

	leds@62 {
		compatible = "nxp,pca9533";
		reg = <0x62>;

		led-1 {
			type = <PCA9532_TYPE_LED>;
		};

		led-2 {
			type = <PCA9532_TYPE_LED>;
		};

		led-3 {
			type = <PCA9532_TYPE_LED>;
		};
	};
};

&lcdif2 {
	status = "okay";
};

&lvds_bridge {
	status = "okay";

	ports {
		port@2 {
			ldb_lvds_ch1: endpoint {
				remote-endpoint = <&panel1_in>;
			};
		};
	};
};

&snvs_pwrkey {
	status = "okay";
};

&pcie_phy {
	clocks = <&hsio_blk_ctrl>;
	clock-names = "ref";
	fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
	fsl,clkreq-unsupported;
	status = "okay";
};

/* Mini PCIe */
&pcie {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie0>;
	reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
	vpcie-supply = <&reg_vcc_3v3_sw>;
	status = "okay";
};

&pwm3 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm3>;
};

&rv3028 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_rtc>;
	interrupt-parent = <&gpio4>;
	interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
	aux-voltage-chargeable = <1>;
	wakeup-source;
	trickle-resistor-ohms = <3000>;
};

/* debug console */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

/* USB1 Host mode Type-A */
&usb3_phy0 {
	vbus-supply = <&reg_usb1_vbus>;
	status = "okay";
};

&usb3_0 {
	status = "okay";
};

&usb_dwc3_0 {
	dr_mode = "host";
	status = "okay";
};

/* USB2 4-port USB3.0 HUB */
&usb3_phy1 {
	vbus-supply = <&reg_vcc_5v_sw>;
	status = "okay";
};

&usb3_1 {
	fsl,permanently-attached;
	fsl,disable-port-power-control;
	status = "okay";
};

&usb_dwc3_1 {
	dr_mode = "host";
	status = "okay";
};

/* RS232/RS485 */
&uart2 {
	assigned-clocks = <&clk IMX8MP_CLK_UART2>;
	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	uart-has-rtscts;
	status = "okay";
};

/* SD-Card */
&usdhc2 {
	assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	disable-wp;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	vqmmc-supply = <&ldo5>;
	bus-width = <4>;
	status = "okay";
};

&gpio1 {
	gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
		"PMIC_SD_VSEL", "", "", "", "", "",
		"", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT";
};

&gpio2 {
	gpio-line-names = "", "", "", "",
		"", "", "", "", "", "",
		"", "", "X_SD2_CD_B", "", "", "",
		"", "", "", "SD2_RESET_B";
};

&gpio3 {
	gpio-line-names = "", "", "", "",
		"", "", "", "", "", "",
		"", "", "", "", "", "",
		"", "", "", "", "nCAN1_EN", "nCAN2_EN";
};

&gpio4 {
	gpio-line-names = "", "", "", "",
		"", "", "", "", "", "",
		"", "", "", "", "", "",
		"", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN";
};

&iomuxc {
	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <
			MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO   0x80
			MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI   0x80
			MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK   0x80
			MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09     0x00
		>;
	};

	pinctrl_eqos: eqosgrp {
		fsl,pins = <
			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC			0x2
			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO			0x2
			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90
			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90
			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90
			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90
			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90
			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x12
			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x12
			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x12
			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x12
			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x12
			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x12
			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20			0x10
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX		0x154
			MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX		0x154
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX		0x154
			MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX		0x154
		>;
	};

	pinctrl_flexcan1_reg: flexcan1reggrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20	0x154
		>;
	};

	pinctrl_flexcan2_reg: flexcan2reggrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21	0x154
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2
			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2
		>;
	};

	pinctrl_i2c2_gpio: i2c2gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16	0x1e2
			MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17	0x1e2
		>;
	};

	pinctrl_lvds1: lvds1grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20		0x12
		>;
	};

	pinctrl_pcie0: pcie0grp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08     0x40
			MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10     0x60
			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11	0x60 /* open drain, pull up */
			MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14     0x40
		>;
	};

	pinctrl_pwm3: pwm3grp {
		fsl,pins = <
			MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT		0x12
		>;
	};

	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
		>;
	};

	pinctrl_rtc: rtcgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x1C0
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
		>;
	};

	pinctrl_usb1_vbus: usb1vbusgrp {
		fsl,pins = <
			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12     0x10
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX	0x140
			MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
			MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS	0x140
			MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS	0x140
		>;
	};

	pinctrl_usdhc2_pins: usdhc2-gpiogrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x40
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x190
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d0
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d0
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d0
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d0
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d0
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x194
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d4
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d4
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d4
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d4
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d4
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
		fsl,pins = <
			MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK	0x196
			MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD	0x1d6
			MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0	0x1d6
			MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1	0x1d6
			MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2	0x1d6
			MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3	0x1d6
			MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT	0xc0
		>;
	};
};