| // SPDX-License-Identifier: GPL-2.0-only OR MIT |
| /* |
| * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals |
| * |
| * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ |
| */ |
| |
| &cbass_mcu_wakeup { |
| sms: system-controller@44083000 { |
| bootph-all; |
| compatible = "ti,k2g-sci"; |
| ti,host-id = <12>; |
| |
| mbox-names = "rx", "tx"; |
| |
| mboxes = <&secure_proxy_main 11>, |
| <&secure_proxy_main 13>; |
| |
| reg-names = "debug_messages"; |
| reg = <0x00 0x44083000 0x00 0x1000>; |
| |
| k3_pds: power-controller { |
| bootph-all; |
| compatible = "ti,sci-pm-domain"; |
| #power-domain-cells = <2>; |
| }; |
| |
| k3_clks: clock-controller { |
| bootph-all; |
| compatible = "ti,k2g-sci-clk"; |
| #clock-cells = <2>; |
| }; |
| |
| k3_reset: reset-controller { |
| bootph-all; |
| compatible = "ti,sci-reset"; |
| #reset-cells = <2>; |
| }; |
| }; |
| |
| wkup_conf: bus@43000000 { |
| bootph-all; |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x00 0x43000000 0x20000>; |
| |
| chipid: chipid@14 { |
| bootph-all; |
| compatible = "ti,am654-chipid"; |
| reg = <0x14 0x4>; |
| }; |
| }; |
| |
| secure_proxy_sa3: mailbox@43600000 { |
| compatible = "ti,am654-secure-proxy"; |
| #mbox-cells = <1>; |
| reg-names = "target_data", "rt", "scfg"; |
| reg = <0x00 0x43600000 0x00 0x10000>, |
| <0x00 0x44880000 0x00 0x20000>, |
| <0x00 0x44860000 0x00 0x20000>; |
| /* |
| * Marked Disabled: |
| * Node is incomplete as it is meant for bootloaders and |
| * firmware on non-MPU processors |
| */ |
| status = "disabled"; |
| }; |
| |
| mcu_ram: sram@41c00000 { |
| compatible = "mmio-sram"; |
| reg = <0x00 0x41c00000 0x00 0x100000>; |
| ranges = <0x00 0x00 0x41c00000 0x100000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| }; |
| |
| wkup_pmx0: pinctrl@4301c000 { |
| compatible = "pinctrl-single"; |
| /* Proxy 0 addressing */ |
| reg = <0x00 0x4301c000 0x00 0x034>; |
| #pinctrl-cells = <1>; |
| pinctrl-single,register-width = <32>; |
| pinctrl-single,function-mask = <0xffffffff>; |
| }; |
| |
| wkup_pmx1: pinctrl@4301c038 { |
| compatible = "pinctrl-single"; |
| /* Proxy 0 addressing */ |
| reg = <0x00 0x4301c038 0x00 0x02c>; |
| #pinctrl-cells = <1>; |
| pinctrl-single,register-width = <32>; |
| pinctrl-single,function-mask = <0xffffffff>; |
| }; |
| |
| wkup_pmx2: pinctrl@4301c068 { |
| compatible = "pinctrl-single"; |
| /* Proxy 0 addressing */ |
| reg = <0x00 0x4301c068 0x00 0x120>; |
| #pinctrl-cells = <1>; |
| pinctrl-single,register-width = <32>; |
| pinctrl-single,function-mask = <0xffffffff>; |
| }; |
| |
| wkup_pmx3: pinctrl@4301c190 { |
| compatible = "pinctrl-single"; |
| /* Proxy 0 addressing */ |
| reg = <0x00 0x4301c190 0x00 0x004>; |
| #pinctrl-cells = <1>; |
| pinctrl-single,register-width = <32>; |
| pinctrl-single,function-mask = <0xffffffff>; |
| }; |
| |
| wkup_gpio_intr: interrupt-controller@42200000 { |
| compatible = "ti,sci-intr"; |
| reg = <0x00 0x42200000 0x00 0x400>; |
| ti,intr-trigger-type = <1>; |
| interrupt-controller; |
| interrupt-parent = <&gic500>; |
| #interrupt-cells = <1>; |
| ti,sci = <&sms>; |
| ti,sci-dev-id = <177>; |
| ti,interrupt-ranges = <16 960 16>; |
| }; |
| |
| /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ |
| mcu_timerio_input: pinctrl@40f04200 { |
| compatible = "pinctrl-single"; |
| reg = <0x00 0x40f04200 0x00 0x28>; |
| #pinctrl-cells = <1>; |
| pinctrl-single,register-width = <32>; |
| pinctrl-single,function-mask = <0x0000000f>; |
| /* Non-MPU Firmware usage */ |
| status = "reserved"; |
| }; |
| |
| /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ |
| mcu_timerio_output: pinctrl@40f04280 { |
| compatible = "pinctrl-single"; |
| reg = <0x00 0x40f04280 0x00 0x28>; |
| #pinctrl-cells = <1>; |
| pinctrl-single,register-width = <32>; |
| pinctrl-single,function-mask = <0x0000000f>; |
| /* Non-MPU Firmware usage */ |
| status = "reserved"; |
| }; |
| |
| mcu_conf: bus@40f00000 { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x0 0x40f00000 0x20000>; |
| |
| cpsw_mac_syscon: ethernet-mac-syscon@200 { |
| compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; |
| reg = <0x200 0x8>; |
| }; |
| |
| phy_gmii_sel: phy@4040 { |
| compatible = "ti,am654-phy-gmii-sel"; |
| reg = <0x4040 0x4>; |
| #phy-cells = <1>; |
| }; |
| }; |
| |
| mcu_timer0: timer@40400000 { |
| compatible = "ti,am654-timer"; |
| reg = <0x00 0x40400000 0x00 0x400>; |
| interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&k3_clks 35 2>; |
| clock-names = "fck"; |
| assigned-clocks = <&k3_clks 35 2>; |
| assigned-clock-parents = <&k3_clks 35 3>; |
| power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; |
| ti,timer-pwm; |
| /* Non-MPU Firmware usage */ |
| status = "reserved"; |
| }; |
| |
| mcu_timer1: timer@40410000 { |
| bootph-all; |
| compatible = "ti,am654-timer"; |
| reg = <0x00 0x40410000 0x00 0x400>; |
| interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&k3_clks 117 2>; |
| clock-names = "fck"; |
| assigned-clocks = <&k3_clks 117 2>; |
| assigned-clock-parents = <&k3_clks 117 3>; |
| power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; |
| ti,timer-pwm; |
| /* Non-MPU Firmware usage */ |
| status = "reserved"; |
| }; |
| |
| mcu_timer2: timer@40420000 { |
| compatible = "ti,am654-timer"; |
| reg = <0x00 0x40420000 0x00 0x400>; |
| interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&k3_clks 118 2>; |
| clock-names = "fck"; |
| assigned-clocks = <&k3_clks 118 2>; |
| assigned-clock-parents = <&k3_clks 118 3>; |
| power-domains = <&k3_pds 118 TI_SCI_PD_EXCLUSIVE>; |
| ti,timer-pwm; |
| /* Non-MPU Firmware usage */ |
| status = "reserved"; |
| }; |
| |
| mcu_timer3: timer@40430000 { |
| compatible = "ti,am654-timer"; |
| reg = <0x00 0x40430000 0x00 0x400>; |
| interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&k3_clks 119 2>; |
| clock-names = "fck"; |
| assigned-clocks = <&k3_clks 119 2>; |
| assigned-clock-parents = <&k3_clks 119 3>; |
| power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; |
| ti,timer-pwm; |
| /* Non-MPU Firmware usage */ |
| status = "reserved"; |
| }; |
| |
| mcu_timer4: timer@40440000 { |
| compatible = "ti,am654-timer"; |
| reg = <0x00 0x40440000 0x00 0x400>; |
| interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&k3_clks 120 2>; |
| clock-names = "fck"; |
| assigned-clocks = <&k3_clks 120 2>; |
| assigned-clock-parents = <&k3_clks 120 3>; |
| power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; |
| ti,timer-pwm; |
| /* Non-MPU Firmware usage */ |
| status = "reserved"; |
| }; |
| |
| mcu_timer5: timer@40450000 { |
| compatible = "ti,am654-timer"; |
| reg = <0x00 0x40450000 0x00 0x400>; |
| interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&k3_clks 121 2>; |
| clock-names = "fck"; |
| assigned-clocks = <&k3_clks 121 2>; |
| assigned-clock-parents = <&k3_clks 121 3>; |
| power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; |
| ti,timer-pwm; |
| /* Non-MPU Firmware usage */ |
| status = "reserved"; |
| }; |
| |
| mcu_timer6: timer@40460000 { |
| compatible = "ti,am654-timer"; |
| reg = <0x00 0x40460000 0x00 0x400>; |
| interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&k3_clks 122 2>; |
| clock-names = "fck"; |
| assigned-clocks = <&k3_clks 122 2>; |
| assigned-clock-parents = <&k3_clks 122 3>; |
| power-domains = <&k3_pds 122 TI_SCI_PD_EXCLUSIVE>; |
| ti,timer-pwm; |
| /* Non-MPU Firmware usage */ |
| status = "reserved"; |
| }; |
| |
| mcu_timer7: timer@40470000 { |
| compatible = "ti,am654-timer"; |
| reg = <0x00 0x40470000 0x00 0x400>; |
| interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&k3_clks 123 2>; |
| clock-names = "fck"; |
| assigned-clocks = <&k3_clks 123 2>; |
| assigned-clock-parents = <&k3_clks 123 3>; |
| power-domains = <&k3_pds 123 TI_SCI_PD_EXCLUSIVE>; |
| ti,timer-pwm; |
| /* Non-MPU Firmware usage */ |
| status = "reserved"; |
| }; |
| |
| mcu_timer8: timer@40480000 { |
| compatible = "ti,am654-timer"; |
| reg = <0x00 0x40480000 0x00 0x400>; |
| interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&k3_clks 124 2>; |
| clock-names = "fck"; |
| assigned-clocks = <&k3_clks 124 2>; |
| assigned-clock-parents = <&k3_clks 124 3>; |
| power-domains = <&k3_pds 124 TI_SCI_PD_EXCLUSIVE>; |
| ti,timer-pwm; |
| /* Non-MPU Firmware usage */ |
| status = "reserved"; |
| }; |
| |
| mcu_timer9: timer@40490000 { |
| compatible = "ti,am654-timer"; |
| reg = <0x00 0x40490000 0x00 0x400>; |
| interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&k3_clks 125 2>; |
| clock-names = "fck"; |
| assigned-clocks = <&k3_clks 125 2>; |
| assigned-clock-parents = <&k3_clks 125 3>; |
| power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; |
| ti,timer-pwm; |
| /* Non-MPU Firmware usage */ |
| status = "reserved"; |
| }; |
| |
| wkup_uart0: serial@42300000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x42300000 0x00 0x200>; |
| interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&k3_clks 397 0>; |
| clock-names = "fclk"; |
| power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>; |
| status = "disabled"; |
| }; |
| |
| mcu_uart0: serial@40a00000 { |
| compatible = "ti,j721e-uart", "ti,am654-uart"; |
| reg = <0x00 0x40a00000 0x00 0x200>; |
| interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&k3_clks 149 0>; |
| clock-names = "fclk"; |
| power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; |
| status = "disabled"; |
| }; |
| |
| wkup_gpio0: gpio@42110000 { |
| compatible = "ti,j721e-gpio", "ti,keystone-gpio"; |
| reg = <0x00 0x42110000 0x00 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&wkup_gpio_intr>; |
| interrupts = <103>, <104>, <105>, <106>, <107>, <108>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <89>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 167 0>; |
| clock-names = "gpio"; |
| status = "disabled"; |
| }; |
| |
| wkup_gpio1: gpio@42100000 { |
| compatible = "ti,j721e-gpio", "ti,keystone-gpio"; |
| reg = <0x00 0x42100000 0x00 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&wkup_gpio_intr>; |
| interrupts = <112>, <113>, <114>, <115>, <116>, <117>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <89>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 168 0>; |
| clock-names = "gpio"; |
| status = "disabled"; |
| }; |
| |
| wkup_i2c0: i2c@42120000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x42120000 0x00 0x100>; |
| interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&k3_clks 279 2>; |
| clock-names = "fck"; |
| power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; |
| status = "disabled"; |
| }; |
| |
| mcu_i2c0: i2c@40b00000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x40b00000 0x00 0x100>; |
| interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&k3_clks 277 2>; |
| clock-names = "fck"; |
| power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; |
| status = "disabled"; |
| }; |
| |
| mcu_i2c1: i2c@40b10000 { |
| compatible = "ti,j721e-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x40b10000 0x00 0x100>; |
| interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&k3_clks 278 2>; |
| clock-names = "fck"; |
| power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; |
| status = "disabled"; |
| }; |
| |
| mcu_mcan0: can@40528000 { |
| compatible = "bosch,m_can"; |
| reg = <0x00 0x40528000 0x00 0x200>, |
| <0x00 0x40500000 0x00 0x8000>; |
| reg-names = "m_can", "message_ram"; |
| power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 263 6>, <&k3_clks 263 1>; |
| clock-names = "hclk", "cclk"; |
| interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "int0", "int1"; |
| bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; |
| status = "disabled"; |
| }; |
| |
| mcu_mcan1: can@40568000 { |
| compatible = "bosch,m_can"; |
| reg = <0x00 0x40568000 0x00 0x200>, |
| <0x00 0x40540000 0x00 0x8000>; |
| reg-names = "m_can", "message_ram"; |
| power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 264 6>, <&k3_clks 264 1>; |
| clock-names = "hclk", "cclk"; |
| interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "int0", "int1"; |
| bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; |
| status = "disabled"; |
| }; |
| |
| mcu_spi0: spi@40300000 { |
| compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; |
| reg = <0x00 0x040300000 0x00 0x400>; |
| interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&k3_pds 384 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 384 0>; |
| status = "disabled"; |
| }; |
| |
| mcu_spi1: spi@40310000 { |
| compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; |
| reg = <0x00 0x040310000 0x00 0x400>; |
| interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&k3_pds 385 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 385 0>; |
| status = "disabled"; |
| }; |
| |
| mcu_spi2: spi@40320000 { |
| compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; |
| reg = <0x00 0x040320000 0x00 0x400>; |
| interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&k3_pds 386 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 386 0>; |
| status = "disabled"; |
| }; |
| |
| mcu_navss: bus@28380000 { |
| bootph-all; |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; |
| ti,sci-dev-id = <323>; |
| dma-coherent; |
| dma-ranges; |
| |
| mcu_ringacc: ringacc@2b800000 { |
| bootph-all; |
| compatible = "ti,am654-navss-ringacc"; |
| reg = <0x00 0x2b800000 0x00 0x400000>, |
| <0x00 0x2b000000 0x00 0x400000>, |
| <0x00 0x28590000 0x00 0x100>, |
| <0x00 0x2a500000 0x00 0x40000>, |
| <0x00 0x28440000 0x00 0x40000>; |
| reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; |
| ti,num-rings = <286>; |
| ti,sci-rm-range-gp-rings = <0x1>; |
| ti,sci = <&sms>; |
| ti,sci-dev-id = <328>; |
| msi-parent = <&main_udmass_inta>; |
| }; |
| |
| mcu_udmap: dma-controller@285c0000 { |
| bootph-all; |
| compatible = "ti,j721e-navss-mcu-udmap"; |
| reg = <0x00 0x285c0000 0x00 0x100>, |
| <0x00 0x2a800000 0x00 0x40000>, |
| <0x00 0x2aa00000 0x00 0x40000>, |
| <0x00 0x284a0000 0x00 0x4000>, |
| <0x00 0x284c0000 0x00 0x4000>, |
| <0x00 0x28400000 0x00 0x2000>; |
| reg-names = "gcfg", "rchanrt", "tchanrt", |
| "tchan", "rchan", "rflow"; |
| msi-parent = <&main_udmass_inta>; |
| #dma-cells = <1>; |
| |
| ti,sci = <&sms>; |
| ti,sci-dev-id = <329>; |
| ti,ringacc = <&mcu_ringacc>; |
| ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ |
| <0x0f>; /* TX_HCHAN */ |
| ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ |
| <0x0b>; /* RX_HCHAN */ |
| ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ |
| }; |
| }; |
| |
| secure_proxy_mcu: mailbox@2a480000 { |
| compatible = "ti,am654-secure-proxy"; |
| #mbox-cells = <1>; |
| reg-names = "target_data", "rt", "scfg"; |
| reg = <0x00 0x2a480000 0x00 0x80000>, |
| <0x00 0x2a380000 0x00 0x80000>, |
| <0x00 0x2a400000 0x00 0x80000>; |
| /* |
| * Marked Disabled: |
| * Node is incomplete as it is meant for bootloaders and |
| * firmware on non-MPU processors |
| */ |
| status = "disabled"; |
| }; |
| |
| mcu_cpsw: ethernet@46000000 { |
| compatible = "ti,j721e-cpsw-nuss"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| reg = <0x00 0x46000000 0x00 0x200000>; |
| reg-names = "cpsw_nuss"; |
| ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; |
| dma-coherent; |
| clocks = <&k3_clks 63 0>; |
| clock-names = "fck"; |
| power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; |
| |
| dmas = <&mcu_udmap 0xf000>, |
| <&mcu_udmap 0xf001>, |
| <&mcu_udmap 0xf002>, |
| <&mcu_udmap 0xf003>, |
| <&mcu_udmap 0xf004>, |
| <&mcu_udmap 0xf005>, |
| <&mcu_udmap 0xf006>, |
| <&mcu_udmap 0xf007>, |
| <&mcu_udmap 0x7000>; |
| dma-names = "tx0", "tx1", "tx2", "tx3", |
| "tx4", "tx5", "tx6", "tx7", |
| "rx"; |
| status = "disabled"; |
| |
| ethernet-ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| mcu_cpsw_port1: port@1 { |
| reg = <1>; |
| ti,mac-only; |
| label = "port1"; |
| ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; |
| phys = <&phy_gmii_sel 1>; |
| }; |
| }; |
| |
| davinci_mdio: mdio@f00 { |
| compatible = "ti,cpsw-mdio","ti,davinci_mdio"; |
| reg = <0x00 0xf00 0x00 0x100>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&k3_clks 63 0>; |
| clock-names = "fck"; |
| bus_freq = <1000000>; |
| }; |
| |
| cpts@3d000 { |
| compatible = "ti,am65-cpts"; |
| reg = <0x00 0x3d000 0x00 0x400>; |
| clocks = <&k3_clks 63 3>; |
| clock-names = "cpts"; |
| assigned-clocks = <&k3_clks 63 3>; /* CPTS_RFT_CLK */ |
| assigned-clock-parents = <&k3_clks 63 5>; /* MAIN_0_HSDIV6_CLK */ |
| interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "cpts"; |
| ti,cpts-ext-ts-inputs = <4>; |
| ti,cpts-periodic-outputs = <2>; |
| }; |
| }; |
| |
| mcu_r5fss0: r5fss@41000000 { |
| compatible = "ti,j721s2-r5fss"; |
| ti,cluster-mode = <1>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x41000000 0x00 0x41000000 0x20000>, |
| <0x41400000 0x00 0x41400000 0x20000>; |
| power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; |
| |
| mcu_r5fss0_core0: r5f@41000000 { |
| compatible = "ti,j721s2-r5f"; |
| reg = <0x41000000 0x00010000>, |
| <0x41010000 0x00010000>; |
| reg-names = "atcm", "btcm"; |
| ti,sci = <&sms>; |
| ti,sci-dev-id = <346>; |
| ti,sci-proc-ids = <0x01 0xff>; |
| resets = <&k3_reset 346 1>; |
| firmware-name = "j784s4-mcu-r5f0_0-fw"; |
| ti,atcm-enable = <1>; |
| ti,btcm-enable = <1>; |
| ti,loczrama = <1>; |
| }; |
| |
| mcu_r5fss0_core1: r5f@41400000 { |
| compatible = "ti,j721s2-r5f"; |
| reg = <0x41400000 0x00010000>, |
| <0x41410000 0x00010000>; |
| reg-names = "atcm", "btcm"; |
| ti,sci = <&sms>; |
| ti,sci-dev-id = <347>; |
| ti,sci-proc-ids = <0x02 0xff>; |
| resets = <&k3_reset 347 1>; |
| firmware-name = "j784s4-mcu-r5f0_1-fw"; |
| ti,atcm-enable = <1>; |
| ti,btcm-enable = <1>; |
| ti,loczrama = <1>; |
| }; |
| }; |
| |
| wkup_vtm0: temperature-sensor@42040000 { |
| compatible = "ti,j7200-vtm"; |
| reg = <0x00 0x42040000 0x00 0x350>, |
| <0x00 0x42050000 0x00 0x350>; |
| power-domains = <&k3_pds 243 TI_SCI_PD_SHARED>; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| tscadc0: tscadc@40200000 { |
| compatible = "ti,am3359-tscadc"; |
| reg = <0x00 0x40200000 0x00 0x1000>; |
| interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 0 0>; |
| assigned-clocks = <&k3_clks 0 2>; |
| assigned-clock-rates = <60000000>; |
| clock-names = "fck"; |
| dmas = <&main_udmap 0x7400>, |
| <&main_udmap 0x7401>; |
| dma-names = "fifo0", "fifo1"; |
| status = "disabled"; |
| |
| adc { |
| #io-channel-cells = <1>; |
| compatible = "ti,am3359-adc"; |
| }; |
| }; |
| |
| tscadc1: tscadc@40210000 { |
| compatible = "ti,am3359-tscadc"; |
| reg = <0x00 0x40210000 0x00 0x1000>; |
| interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 1 0>; |
| assigned-clocks = <&k3_clks 1 2>; |
| assigned-clock-rates = <60000000>; |
| clock-names = "fck"; |
| dmas = <&main_udmap 0x7402>, |
| <&main_udmap 0x7403>; |
| dma-names = "fifo0", "fifo1"; |
| status = "disabled"; |
| |
| adc { |
| #io-channel-cells = <1>; |
| compatible = "ti,am3359-adc"; |
| }; |
| }; |
| |
| fss: bus@47000000 { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00000100>, /* FSS Control */ |
| <0x00 0x47040000 0x00 0x47040000 0x00 0x00000100>, /* OSPI0 Control */ |
| <0x00 0x47050000 0x00 0x47050000 0x00 0x00000100>, /* OSPI1 Control */ |
| <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */ |
| <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */ |
| |
| ospi0: spi@47040000 { |
| compatible = "ti,am654-ospi", "cdns,qspi-nor"; |
| reg = <0x00 0x47040000 0x00 0x100>, |
| <0x05 0x00000000 0x01 0x00000000>; |
| interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; |
| cdns,fifo-depth = <256>; |
| cdns,fifo-width = <4>; |
| cdns,trigger-address = <0x0>; |
| clocks = <&k3_clks 161 7>; |
| assigned-clocks = <&k3_clks 161 7>; |
| assigned-clock-parents = <&k3_clks 161 9>; |
| assigned-clock-rates = <166666666>; |
| power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| ospi1: spi@47050000 { |
| compatible = "ti,am654-ospi", "cdns,qspi-nor"; |
| reg = <0x00 0x47050000 0x00 0x100>, |
| <0x07 0x00000000 0x01 0x00000000>; |
| interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; |
| cdns,fifo-depth = <256>; |
| cdns,fifo-width = <4>; |
| cdns,trigger-address = <0x0>; |
| clocks = <&k3_clks 162 7>; |
| power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| }; |
| |
| mcu_esm: esm@40800000 { |
| compatible = "ti,j721e-esm"; |
| reg = <0x00 0x40800000 0x00 0x1000>; |
| ti,esm-pins = <95>; |
| bootph-pre-ram; |
| }; |
| |
| wkup_esm: esm@42080000 { |
| compatible = "ti,j721e-esm"; |
| reg = <0x00 0x42080000 0x00 0x1000>; |
| ti,esm-pins = <63>; |
| bootph-pre-ram; |
| }; |
| |
| /* |
| * The 2 RTI instances are couple with MCU R5Fs so keeping them |
| * reserved as these will be used by their respective firmware |
| */ |
| mcu_watchdog0: watchdog@40600000 { |
| compatible = "ti,j7-rti-wdt"; |
| reg = <0x00 0x40600000 0x00 0x100>; |
| clocks = <&k3_clks 367 1>; |
| power-domains = <&k3_pds 367 TI_SCI_PD_EXCLUSIVE>; |
| assigned-clocks = <&k3_clks 367 0>; |
| assigned-clock-parents = <&k3_clks 367 4>; |
| /* reserved for MCU_R5F0_0 */ |
| status = "reserved"; |
| }; |
| |
| mcu_watchdog1: watchdog@40610000 { |
| compatible = "ti,j7-rti-wdt"; |
| reg = <0x00 0x40610000 0x00 0x100>; |
| clocks = <&k3_clks 368 1>; |
| power-domains = <&k3_pds 368 TI_SCI_PD_EXCLUSIVE>; |
| assigned-clocks = <&k3_clks 368 0>; |
| assigned-clock-parents = <&k3_clks 368 4>; |
| /* reserved for MCU_R5F0_1 */ |
| status = "reserved"; |
| }; |
| }; |
