tree 56a8aedbbe9d8f266e4d8a8405aa3dee79c36f3e
parent fbc6ae363e5e589a28135c051a2ff835e6236d5f
author Aaron Sierra <asierra@xes-inc.com> 1359060759 -0600
committer Samuel Ortiz <sameo@linux.intel.com> 1360797772 +0100

mfd: lpc_ich: Fix gpio base and control offsets

In ICH5 and earlier the GPIOBASE and GPIOCTRL registers are found at
offsets 0x58 and 0x5C, respectively. This patch allows GPIO access to
properly be enabled (and disabled) for these chipsets.

Signed-off-by: Agócs Pál <agocs.pal.86@gmail.com>
Signed-off-by: Aaron Sierra <asierra@xes-inc.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>