/* Only for QMP V5 PHY - UFS PCS registers */
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
 */

#ifndef QCOM_PHY_QMP_PCS_UFS_V5_H_
#define QCOM_PHY_QMP_PCS_UFS_V5_H_

/* Only for QMP V5 PHY - UFS PCS registers */
#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB	0x00c
#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB	0x010
#define QPHY_V5_PCS_UFS_PLL_CNTL			0x02c
#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL		0x030
#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL		0x038
#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY		0x074
#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY		0x0b4
#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL		0x124
#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME		0x150
#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1			0x154
#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2			0x158
#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND		0x160
#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND			0x168
#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1		0x1d8
#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1		0x1e0

#endif