// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2021 Alibaba Group Holding Limited.
 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/thead,th1520-clk-ap.h>

/ {
	compatible = "thead,th1520";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <3000000>;

		c910_0: cpu@0 {
			compatible = "thead,c910", "riscv";
			device_type = "cpu";
			riscv,isa = "rv64imafdc";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
					       "zifencei", "zihpm";
			reg = <0>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			next-level-cache = <&l2_cache>;
			mmu-type = "riscv,sv39";

			cpu0_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		c910_1: cpu@1 {
			compatible = "thead,c910", "riscv";
			device_type = "cpu";
			riscv,isa = "rv64imafdc";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
					       "zifencei", "zihpm";
			reg = <1>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			next-level-cache = <&l2_cache>;
			mmu-type = "riscv,sv39";

			cpu1_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		c910_2: cpu@2 {
			compatible = "thead,c910", "riscv";
			device_type = "cpu";
			riscv,isa = "rv64imafdc";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
					       "zifencei", "zihpm";
			reg = <2>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			next-level-cache = <&l2_cache>;
			mmu-type = "riscv,sv39";

			cpu2_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		c910_3: cpu@3 {
			compatible = "thead,c910", "riscv";
			device_type = "cpu";
			riscv,isa = "rv64imafdc";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
					       "zifencei", "zihpm";
			reg = <3>;
			i-cache-block-size = <64>;
			i-cache-size = <65536>;
			i-cache-sets = <512>;
			d-cache-block-size = <64>;
			d-cache-size = <65536>;
			d-cache-sets = <512>;
			next-level-cache = <&l2_cache>;
			mmu-type = "riscv,sv39";

			cpu3_intc: interrupt-controller {
				compatible = "riscv,cpu-intc";
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};

		l2_cache: l2-cache {
			compatible = "cache";
			cache-block-size = <64>;
			cache-level = <2>;
			cache-size = <1048576>;
			cache-sets = <1024>;
			cache-unified;
		};
	};

	pmu {
		compatible = "riscv,pmu";
		riscv,event-to-mhpmcounters =
			<0x00003 0x00003 0x0007fff8>,
			<0x00004 0x00004 0x0007fff8>,
			<0x00005 0x00005 0x0007fff8>,
			<0x00006 0x00006 0x0007fff8>,
			<0x00007 0x00007 0x0007fff8>,
			<0x00008 0x00008 0x0007fff8>,
			<0x00009 0x00009 0x0007fff8>,
			<0x0000a 0x0000a 0x0007fff8>,
			<0x10000 0x10000 0x0007fff8>,
			<0x10001 0x10001 0x0007fff8>,
			<0x10002 0x10002 0x0007fff8>,
			<0x10003 0x10003 0x0007fff8>,
			<0x10010 0x10010 0x0007fff8>,
			<0x10011 0x10011 0x0007fff8>,
			<0x10012 0x10012 0x0007fff8>,
			<0x10013 0x10013 0x0007fff8>;
		riscv,event-to-mhpmevent =
			<0x00003 0x00000000 0x00000001>,
			<0x00004 0x00000000 0x00000002>,
			<0x00006 0x00000000 0x00000006>,
			<0x00005 0x00000000 0x00000007>,
			<0x00007 0x00000000 0x00000008>,
			<0x00008 0x00000000 0x00000009>,
			<0x00009 0x00000000 0x0000000a>,
			<0x0000a 0x00000000 0x0000000b>,
			<0x10000 0x00000000 0x0000000c>,
			<0x10001 0x00000000 0x0000000d>,
			<0x10002 0x00000000 0x0000000e>,
			<0x10003 0x00000000 0x0000000f>,
			<0x10010 0x00000000 0x00000010>,
			<0x10011 0x00000000 0x00000011>,
			<0x10012 0x00000000 0x00000012>,
			<0x10013 0x00000000 0x00000013>;
		riscv,raw-event-to-mhpmcounters =
			<0x00000000 0x00000001 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000002 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000003 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000004 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000005 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000006 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000007 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000008 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000009 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x0000000a 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x0000000b 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x0000000c 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x0000000d 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000010 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000011 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000012 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000013 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000014 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000015 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000016 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000017 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000018 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000019 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x0000001a 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x0000001b 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x0000001c 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x0000001d 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x0000001e 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x0000001f 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000020 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000021 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000022 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000023 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000024 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000025 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000026 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000027 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000028 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x00000029 0xffffffff 0xffffffff 0x0007fff8>,
			<0x00000000 0x0000002a 0xffffffff 0xffffffff 0x0007fff8>;
	};

	osc: oscillator {
		compatible = "fixed-clock";
		clock-output-names = "osc_24m";
		#clock-cells = <0>;
	};

	osc_32k: 32k-oscillator {
		compatible = "fixed-clock";
		clock-output-names = "osc_32k";
		#clock-cells = <0>;
	};

	apb_clk: apb-clk-clock {
		compatible = "fixed-clock";
		clock-output-names = "apb_clk";
		#clock-cells = <0>;
	};

	spi_clk: spi-clock {
		compatible = "fixed-clock";
		clock-output-names = "spi_clk";
		#clock-cells = <0>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&plic>;
		#address-cells = <2>;
		#size-cells = <2>;
		dma-noncoherent;
		ranges;

		plic: interrupt-controller@ffd8000000 {
			compatible = "thead,th1520-plic", "thead,c900-plic";
			reg = <0xff 0xd8000000 0x0 0x01000000>;
			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
					      <&cpu1_intc 11>, <&cpu1_intc 9>,
					      <&cpu2_intc 11>, <&cpu2_intc 9>,
					      <&cpu3_intc 11>, <&cpu3_intc 9>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			riscv,ndev = <240>;
		};

		clint: timer@ffdc000000 {
			compatible = "thead,th1520-clint", "thead,c900-clint";
			reg = <0xff 0xdc000000 0x0 0x00010000>;
			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
					      <&cpu1_intc 3>, <&cpu1_intc 7>,
					      <&cpu2_intc 3>, <&cpu2_intc 7>,
					      <&cpu3_intc 3>, <&cpu3_intc 7>;
		};

		spi0: spi@ffe700c000 {
			compatible = "thead,th1520-spi", "snps,dw-apb-ssi";
			reg = <0xff 0xe700c000 0x0 0x1000>;
			interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&spi_clk>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		uart0: serial@ffe7014000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xe7014000 0x0 0x100>;
			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>;
			clock-names = "baudclk", "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		emmc: mmc@ffe7080000 {
			compatible = "thead,th1520-dwcmshc";
			reg = <0xff 0xe7080000 0x0 0x10000>;
			interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk CLK_EMMC_SDIO>;
			clock-names = "core";
			status = "disabled";
		};

		sdio0: mmc@ffe7090000 {
			compatible = "thead,th1520-dwcmshc";
			reg = <0xff 0xe7090000 0x0 0x10000>;
			interrupts = <64 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk CLK_EMMC_SDIO>;
			clock-names = "core";
			status = "disabled";
		};

		sdio1: mmc@ffe70a0000 {
			compatible = "thead,th1520-dwcmshc";
			reg = <0xff 0xe70a0000 0x0 0x10000>;
			interrupts = <71 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk CLK_EMMC_SDIO>;
			clock-names = "core";
			status = "disabled";
		};

		uart1: serial@ffe7f00000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xe7f00000 0x0 0x100>;
			interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>;
			clock-names = "baudclk", "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		uart3: serial@ffe7f04000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xe7f04000 0x0 0x100>;
			interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>;
			clock-names = "baudclk", "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		gpio2: gpio@ffe7f34000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xe7f34000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			portc: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio3: gpio@ffe7f38000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xe7f38000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			portd: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio0: gpio@ffec005000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xec005000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpio1: gpio@ffec006000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xec006000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		uart2: serial@ffec010000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xec010000 0x0 0x4000>;
			interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>;
			clock-names = "baudclk", "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		clk: clock-controller@ffef010000 {
			compatible = "thead,th1520-clk-ap";
			reg = <0xff 0xef010000 0x0 0x1000>;
			clocks = <&osc>;
			#clock-cells = <1>;
		};

		dmac0: dma-controller@ffefc00000 {
			compatible = "snps,axi-dma-1.01a";
			reg = <0xff 0xefc00000 0x0 0x1000>;
			interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&apb_clk>, <&apb_clk>;
			clock-names = "core-clk", "cfgr-clk";
			#dma-cells = <1>;
			dma-channels = <4>;
			snps,block-size = <65536 65536 65536 65536>;
			snps,priority = <0 1 2 3>;
			snps,dma-masters = <1>;
			snps,data-width = <4>;
			snps,axi-max-burst-len = <16>;
			status = "disabled";
		};

		timer0: timer@ffefc32000 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xefc32000 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer1: timer@ffefc32014 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xefc32014 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer2: timer@ffefc32028 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xefc32028 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer3: timer@ffefc3203c {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xefc3203c 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart4: serial@fff7f08000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xf7f08000 0x0 0x4000>;
			interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>;
			clock-names = "baudclk", "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		uart5: serial@fff7f0c000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xff 0xf7f0c000 0x0 0x4000>;
			interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>;
			clock-names = "baudclk", "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		timer4: timer@ffffc33000 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xffc33000 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer5: timer@ffffc33014 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xffc33014 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer6: timer@ffffc33028 {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xffc33028 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		timer7: timer@ffffc3303c {
			compatible = "snps,dw-apb-timer";
			reg = <0xff 0xffc3303c 0x0 0x14>;
			clocks = <&apb_clk>;
			clock-names = "timer";
			interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		ao_gpio0: gpio@fffff41000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xfff41000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			porte: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		ao_gpio1: gpio@fffff52000 {
			compatible = "snps,dw-apb-gpio";
			reg = <0xff 0xfff52000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;

			portf: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};