| /* SPDX-License-Identifier: GPL-2.0 */ |
| #ifndef __DT_BINDINGS_POWER_RK3568_POWER_H__ |
| #define __DT_BINDINGS_POWER_RK3568_POWER_H__ |
| |
| /* VD_CORE */ |
| #define RK3568_PD_CPU_0 0 |
| #define RK3568_PD_CPU_1 1 |
| #define RK3568_PD_CPU_2 2 |
| #define RK3568_PD_CPU_3 3 |
| #define RK3568_PD_CORE_ALIVE 4 |
| |
| /* VD_PMU */ |
| #define RK3568_PD_PMU 5 |
| |
| /* VD_NPU */ |
| #define RK3568_PD_NPU 6 |
| |
| /* VD_GPU */ |
| #define RK3568_PD_GPU 7 |
| |
| /* VD_LOGIC */ |
| #define RK3568_PD_VI 8 |
| #define RK3568_PD_VO 9 |
| #define RK3568_PD_RGA 10 |
| #define RK3568_PD_VPU 11 |
| #define RK3568_PD_CENTER 12 |
| #define RK3568_PD_RKVDEC 13 |
| #define RK3568_PD_RKVENC 14 |
| #define RK3568_PD_PIPE 15 |
| #define RK3568_PD_LOGIC_ALIVE 16 |
| |
| #endif |
