)]}'
{
  "commit": "079f4532008e21d40a2c43eb32df0fdf7d8dbddc",
  "tree": "8d354748e59c7bdec762a037bb088892bd45a529",
  "parents": [
    "548ce8156f9dc5ca3e09c18f4d5307918a2645b4"
  ],
  "author": {
    "name": "Miquel Raynal",
    "email": "miquel.raynal@bootlin.com",
    "time": "Mon Oct 01 16:13:55 2018 +0200"
  },
  "committer": {
    "name": "Marc Zyngier",
    "email": "marc.zyngier@arm.com",
    "time": "Tue Oct 02 12:02:43 2018 +0100"
  },
  "message": "dt-bindings/interrupt-controller: Add documentation for Marvell SEI controller\n\nDescribe the System Error Interrupt (SEI) controller. It aggregates two\ntypes of interrupts, wired and MSIs from respectively the AP and the\nCPs, into a single SPI interrupt.\n\nSuggested-by: Haim Boot \u003chayim@marvell.com\u003e\nReviewed-by: Rob Herring \u003crobh@kernel.org\u003e\nSigned-off-by: Miquel Raynal \u003cmiquel.raynal@bootlin.com\u003e\nSigned-off-by: Marc Zyngier \u003cmarc.zyngier@arm.com\u003e\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "0beafed502f56a17d4eb6fe24d8674dea5b21558",
      "new_mode": 33188,
      "new_path": "Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt"
    }
  ]
}