| commit | 0873305e68ac2a4665f1f3d27bb0b98a4312e5bd | [log] [tgz] |
|---|---|---|
| author | Geert Uytterhoeven <geert+renesas@glider.be> | Thu Mar 29 11:02:42 2018 +0200 |
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | Mon Apr 16 13:39:49 2018 +0200 |
| tree | a28d97a31bbce2f5455a6b7384bcd453690df31c | |
| parent | 6041ce57f2c8c231017a1b4f7a71b606bb1c1016 [diff] |
clk: renesas: r8a7792: Fix LB clock divider The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where the LB clock divider depends on the value of the MD18 pin. On R-Car V2H, the LB clock divider is fixed to 24. Hence model the clock as a fixed factor clock instead. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>