/*
 * Copyright (c) 2014 MediaTek Inc.
 * Author: Eddie Huang <eddie.huang@mediatek.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "mediatek,mt8173";
	interrupt-parent = <&sysirq>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu2>;
				};
				core1 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x001>;
			enable-method = "psci";
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x100>;
			enable-method = "psci";
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x101>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci";
		method = "smc";
		cpu_suspend   = <0x84000001>;
		cpu_off	      = <0x84000002>;
		cpu_on	      = <0x84000003>;
	};

	uart_clk: dummy26m {
		compatible = "fixed-clock";
		clock-frequency = <26000000>;
		#clock-cells = <0>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	soc {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		ranges;

		sysirq: intpol-controller@10200620 {
			compatible = "mediatek,mt8173-sysirq",
					"mediatek,mt6577-sysirq";
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			reg = <0 0x10200620 0 0x20>;
		};

		gic: interrupt-controller@10220000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-parent = <&gic>;
			interrupt-controller;
			reg = <0 0x10221000 0 0x1000>,
			      <0 0x10222000 0 0x2000>,
			      <0 0x10224000 0 0x2000>,
			      <0 0x10226000 0 0x2000>;
			interrupts = <GIC_PPI 9
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		uart0: serial@11002000 {
			compatible = "mediatek,mt8173-uart",
					"mediatek,mt6577-uart";
			reg = <0 0x11002000 0 0x400>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart1: serial@11003000 {
			compatible = "mediatek,mt8173-uart",
					"mediatek,mt6577-uart";
			reg = <0 0x11003000 0 0x400>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart2: serial@11004000 {
			compatible = "mediatek,mt8173-uart",
					"mediatek,mt6577-uart";
			reg = <0 0x11004000 0 0x400>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};

		uart3: serial@11005000 {
			compatible = "mediatek,mt8173-uart",
					"mediatek,mt6577-uart";
			reg = <0 0x11005000 0 0x400>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
			clocks = <&uart_clk>;
			status = "disabled";
		};
	};

};