// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright 2011-2012 Calxeda, Inc.
 */

/dts-v1/;

/* First 4KB has pen for secondary cores. */
/memreserve/ 0x00000000 0x0001000;

/ {
	model = "Calxeda ECX-2000";
	compatible = "calxeda,ecx-2000";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <0>;
			clocks = <&a9pll>;
			clock-names = "cpu";
		};

		cpu@1 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <1>;
			clocks = <&a9pll>;
			clock-names = "cpu";
		};

		cpu@2 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <2>;
			clocks = <&a9pll>;
			clock-names = "cpu";
		};

		cpu@3 {
			compatible = "arm,cortex-a15";
			device_type = "cpu";
			reg = <3>;
			clocks = <&a9pll>;
			clock-names = "cpu";
		};
	};

	memory@0 {
		name = "memory";
		device_type = "memory";
		reg = <0x00000000 0x00000000 0x00000000 0xff800000>;
	};

	memory@200000000 {
		name = "memory";
		device_type = "memory";
		reg = <0x00000002 0x00000000 0x00000003 0x00000000>;
	};

	soc {
		ranges = <0x00000000 0x00000000 0x00000000 0xffffffff>;

		timer {
			compatible = "arm,cortex-a15-timer", "arm,armv7-timer"; 			interrupts = <1 13 0xf08>,
				<1 14 0xf08>,
				<1 11 0xf08>,
				<1 10 0xf08>;
		};

		memory-controller@fff00000 {
			compatible = "calxeda,ecx-2000-ddr-ctrl";
			reg = <0xfff00000 0x1000>;
			interrupts = <0 91 4>;
		};

		intc: interrupt-controller@fff11000 {
			compatible = "arm,cortex-a15-gic";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			interrupts = <1 9 0xf04>;
			reg = <0xfff11000 0x1000>,
			      <0xfff12000 0x2000>,
			      <0xfff14000 0x2000>,
			      <0xfff16000 0x2000>;
		};

		pmu {
			compatible = "arm,cortex-a9-pmu";
			interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
		};
	};
};

/include/ "ecx-common.dtsi"