| /* SPDX-License-Identifier: GPL-2.0-only */ |
| /* |
| * DRA7xx CM2 instance offset macros |
| * |
| * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com |
| * |
| * Generated by code originally written by: |
| * Paul Walmsley (paul@pwsan.com) |
| * Rajendra Nayak (rnayak@ti.com) |
| * Benoit Cousson (b-cousson@ti.com) |
| * |
| * This file is automatically generated from the OMAP hardware databases. |
| * We respectfully ask that any modifications to this file be coordinated |
| * with the public linux-omap@vger.kernel.org mailing list and the |
| * authors above to ensure that the autogeneration scripts are kept |
| * up-to-date with the file contents. |
| */ |
| |
| #ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H |
| #define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H |
| |
| /* CM2 base address */ |
| #define DRA7XX_CM_CORE_BASE 0x4a008000 |
| |
| #define DRA7XX_CM_CORE_REGADDR(inst, reg) \ |
| OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg)) |
| |
| /* CM_CORE instances */ |
| #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000 |
| #define DRA7XX_CM_CORE_CKGEN_INST 0x0104 |
| #define DRA7XX_CM_CORE_COREAON_INST 0x0600 |
| #define DRA7XX_CM_CORE_CORE_INST 0x0700 |
| #define DRA7XX_CM_CORE_IVA_INST 0x0f00 |
| #define DRA7XX_CM_CORE_CAM_INST 0x1000 |
| #define DRA7XX_CM_CORE_DSS_INST 0x1100 |
| #define DRA7XX_CM_CORE_GPU_INST 0x1200 |
| #define DRA7XX_CM_CORE_L3INIT_INST 0x1300 |
| #define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600 |
| #define DRA7XX_CM_CORE_L4PER_INST 0x1700 |
| #define DRA7XX_CM_CORE_RESTORE_INST 0x1e18 |
| |
| /* CM_CORE clockdomain register offsets (from instance start) */ |
| #define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 |
| #define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000 |
| #define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS 0x0200 |
| #define DRA7XX_CM_CORE_CORE_DMA_CDOFFS 0x0300 |
| #define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400 |
| #define DRA7XX_CM_CORE_CORE_ATL_CDOFFS 0x0520 |
| #define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600 |
| #define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700 |
| #define DRA7XX_CM_CORE_IVA_IVA_CDOFFS 0x0000 |
| #define DRA7XX_CM_CORE_CAM_CAM_CDOFFS 0x0000 |
| #define DRA7XX_CM_CORE_DSS_DSS_CDOFFS 0x0000 |
| #define DRA7XX_CM_CORE_GPU_GPU_CDOFFS 0x0000 |
| #define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 |
| #define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS 0x00a0 |
| #define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS 0x00c0 |
| #define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 |
| #define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS 0x0000 |
| #define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS 0x0180 |
| #define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc |
| #define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210 |
| |
| /* CM_CORE */ |
| |
| /* CM_CORE.OCP_SOCKET_CM_CORE register offsets */ |
| #define DRA7XX_REVISION_CM_CORE_OFFSET 0x0000 |
| #define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040 |
| #define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040) |
| #define DRA7XX_CM_CORE_DEBUG_CFG_OFFSET 0x00f0 |
| |
| /* CM_CORE.CKGEN_CM_CORE register offsets */ |
| #define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0000 |
| #define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000) |
| #define DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET 0x003c |
| #define DRA7XX_CM_CLKMODE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c) |
| #define DRA7XX_CM_IDLEST_DPLL_PER_OFFSET 0x0040 |
| #define DRA7XX_CM_IDLEST_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040) |
| #define DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0044 |
| #define DRA7XX_CM_AUTOIDLE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044) |
| #define DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET 0x0048 |
| #define DRA7XX_CM_CLKSEL_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048) |
| #define DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET 0x004c |
| #define DRA7XX_CM_DIV_M2_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c) |
| #define DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0050 |
| #define DRA7XX_CM_DIV_M3_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050) |
| #define DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0054 |
| #define DRA7XX_CM_DIV_H11_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054) |
| #define DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET 0x0058 |
| #define DRA7XX_CM_DIV_H12_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058) |
| #define DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET 0x005c |
| #define DRA7XX_CM_DIV_H13_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c) |
| #define DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0060 |
| #define DRA7XX_CM_DIV_H14_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060) |
| #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0064 |
| #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0068 |
| #define DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET 0x007c |
| #define DRA7XX_CM_CLKMODE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c) |
| #define DRA7XX_CM_IDLEST_DPLL_USB_OFFSET 0x0080 |
| #define DRA7XX_CM_IDLEST_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080) |
| #define DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0084 |
| #define DRA7XX_CM_AUTOIDLE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084) |
| #define DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET 0x0088 |
| #define DRA7XX_CM_CLKSEL_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088) |
| #define DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET 0x008c |
| #define DRA7XX_CM_DIV_M2_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c) |
| #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a4 |
| #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00a8 |
| #define DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b0 |
| #define DRA7XX_CM_CLKDCOLDO_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0) |
| #define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET 0x00fc |
| #define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc) |
| #define DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET 0x0100 |
| #define DRA7XX_CM_IDLEST_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100) |
| #define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET 0x0104 |
| #define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104) |
| #define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET 0x0108 |
| #define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108) |
| #define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET 0x010c |
| #define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c) |
| #define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET 0x0110 |
| #define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET 0x0114 |
| #define DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET 0x0118 |
| #define DRA7XX_CM_CLKMODE_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118) |
| #define DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET 0x011c |
| #define DRA7XX_CM_IDLEST_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c) |
| #define DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET 0x0120 |
| #define DRA7XX_CM_DIV_M2_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120) |
| #define DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET 0x0124 |
| #define DRA7XX_CM_CLKVCOLDO_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124) |
| |
| /* CM_CORE.COREAON_CM_CORE register offsets */ |
| #define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000 |
| #define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028 |
| #define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028) |
| #define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038 |
| #define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038) |
| #define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET 0x0040 |
| #define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040) |
| #define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050 |
| #define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050) |
| #define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET 0x0058 |
| #define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058) |
| #define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET 0x0068 |
| #define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068) |
| #define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET 0x0078 |
| #define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078) |
| #define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET 0x0088 |
| #define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088) |
| #define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET 0x0098 |
| #define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098) |
| #define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET 0x00a0 |
| #define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0) |
| #define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET 0x00b0 |
| #define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0) |
| #define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET 0x00c0 |
| #define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0) |
| #define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET 0x00d0 |
| #define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0) |
| |
| /* CM_CORE.CORE_CM_CORE register offsets */ |
| #define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000 |
| #define DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008 |
| #define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020 |
| #define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020) |
| #define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET 0x0028 |
| #define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028) |
| #define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET 0x0030 |
| #define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030) |
| #define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET 0x0050 |
| #define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050) |
| #define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET 0x0058 |
| #define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058) |
| #define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET 0x0060 |
| #define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060) |
| #define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET 0x0068 |
| #define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068) |
| #define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET 0x0070 |
| #define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070) |
| #define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET 0x0078 |
| #define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078) |
| #define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET 0x0080 |
| #define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080) |
| #define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET 0x0088 |
| #define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088) |
| #define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET 0x0090 |
| #define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090) |
| #define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET 0x0098 |
| #define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098) |
| #define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET 0x00a0 |
| #define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0) |
| #define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET 0x00a8 |
| #define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8) |
| #define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET 0x00b0 |
| #define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0) |
| #define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET 0x00b8 |
| #define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8) |
| #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET 0x00c0 |
| #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0) |
| #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET 0x00c8 |
| #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8) |
| #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET 0x00d0 |
| #define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0) |
| #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET 0x00d8 |
| #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8) |
| #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET 0x00f0 |
| #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0) |
| #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET 0x00f8 |
| #define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8) |
| #define DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET 0x0200 |
| #define DRA7XX_CM_IPU2_STATICDEP_OFFSET 0x0204 |
| #define DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET 0x0208 |
| #define DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET 0x0220 |
| #define DRA7XX_CM_IPU2_IPU2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220) |
| #define DRA7XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300 |
| #define DRA7XX_CM_DMA_STATICDEP_OFFSET 0x0304 |
| #define DRA7XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308 |
| #define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320 |
| #define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320) |
| #define DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400 |
| #define DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420 |
| #define DRA7XX_CM_EMIF_DMM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420) |
| #define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428 |
| #define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428) |
| #define DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430 |
| #define DRA7XX_CM_EMIF_EMIF1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430) |
| #define DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438 |
| #define DRA7XX_CM_EMIF_EMIF2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438) |
| #define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440 |
| #define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440) |
| #define DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET 0x0500 |
| #define DRA7XX_CM_ATL_ATL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500) |
| #define DRA7XX_CM_ATL_CLKSTCTRL_OFFSET 0x0520 |
| #define DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 |
| #define DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 |
| #define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 |
| #define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620) |
| #define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628 |
| #define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628) |
| #define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET 0x0630 |
| #define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630) |
| #define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 |
| #define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638) |
| #define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640 |
| #define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640) |
| #define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET 0x0648 |
| #define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648) |
| #define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET 0x0650 |
| #define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650) |
| #define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET 0x0658 |
| #define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658) |
| #define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET 0x0660 |
| #define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660) |
| #define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET 0x0668 |
| #define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668) |
| #define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET 0x0670 |
| #define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670) |
| #define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET 0x0678 |
| #define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678) |
| #define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET 0x0680 |
| #define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680) |
| #define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET 0x0688 |
| #define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688) |
| #define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET 0x0690 |
| #define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690) |
| #define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET 0x0698 |
| #define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698) |
| #define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET 0x06a0 |
| #define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0) |
| #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET 0x06a8 |
| #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8) |
| #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET 0x06b0 |
| #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0) |
| #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET 0x06b8 |
| #define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8) |
| #define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET 0x06c0 |
| #define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0) |
| #define DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 |
| #define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET 0x0720 |
| #define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720) |
| #define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 |
| #define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728) |
| #define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740 |
| #define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740) |
| #define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748 |
| #define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748) |
| #define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750 |
| #define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750) |
| |
| /* CM_CORE.IVA_CM_CORE register offsets */ |
| #define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000 |
| #define DRA7XX_CM_IVA_STATICDEP_OFFSET 0x0004 |
| #define DRA7XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008 |
| #define DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020 |
| #define DRA7XX_CM_IVA_IVA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020) |
| #define DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028 |
| #define DRA7XX_CM_IVA_SL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028) |
| |
| /* CM_CORE.CAM_CM_CORE register offsets */ |
| #define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000 |
| #define DRA7XX_CM_CAM_STATICDEP_OFFSET 0x0004 |
| #define DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET 0x0020 |
| #define DRA7XX_CM_CAM_VIP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020) |
| #define DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET 0x0028 |
| #define DRA7XX_CM_CAM_VIP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028) |
| #define DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET 0x0030 |
| #define DRA7XX_CM_CAM_VIP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030) |
| #define DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET 0x0038 |
| #define DRA7XX_CM_CAM_LVDSRX_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038) |
| #define DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET 0x0040 |
| #define DRA7XX_CM_CAM_CSI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040) |
| #define DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET 0x0048 |
| #define DRA7XX_CM_CAM_CSI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048) |
| |
| /* CM_CORE.DSS_CM_CORE register offsets */ |
| #define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000 |
| #define DRA7XX_CM_DSS_STATICDEP_OFFSET 0x0004 |
| #define DRA7XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008 |
| #define DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 |
| #define DRA7XX_CM_DSS_DSS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020) |
| #define DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030 |
| #define DRA7XX_CM_DSS_BB2D_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030) |
| #define DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET 0x003c |
| #define DRA7XX_CM_DSS_SDVENC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c) |
| |
| /* CM_CORE.GPU_CM_CORE register offsets */ |
| #define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000 |
| #define DRA7XX_CM_GPU_STATICDEP_OFFSET 0x0004 |
| #define DRA7XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008 |
| #define DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020 |
| #define DRA7XX_CM_GPU_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020) |
| |
| /* CM_CORE.L3INIT_CM_CORE register offsets */ |
| #define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 |
| #define DRA7XX_CM_L3INIT_STATICDEP_OFFSET 0x0004 |
| #define DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 |
| #define DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 |
| #define DRA7XX_CM_L3INIT_MMC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028) |
| #define DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 |
| #define DRA7XX_CM_L3INIT_MMC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030) |
| #define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET 0x0040 |
| #define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040) |
| #define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET 0x0048 |
| #define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048) |
| #define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET 0x0050 |
| #define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050) |
| #define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET 0x0058 |
| #define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058) |
| #define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078 |
| #define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078) |
| #define DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 |
| #define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088) |
| #define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0 |
| #define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4 |
| #define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET 0x00b0 |
| #define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0) |
| #define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET 0x00b8 |
| #define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8) |
| #define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0 |
| #define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4 |
| #define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8 |
| #define DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET 0x00d0 |
| #define DRA7XX_CM_GMAC_GMAC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0) |
| #define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0 |
| #define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0) |
| #define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8 |
| #define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8) |
| #define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET 0x00f0 |
| #define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0) |
| |
| /* CM_CORE.CUSTEFUSE_CM_CORE register offsets */ |
| #define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000 |
| #define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020 |
| #define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020) |
| |
| /* CM_CORE.L4PER_CM_CORE register offsets */ |
| #define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 |
| #define DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 |
| #define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET 0x000c |
| #define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c) |
| #define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET 0x0014 |
| #define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014) |
| #define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET 0x0018 |
| #define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018) |
| #define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET 0x0020 |
| #define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020) |
| #define DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0028 |
| #define DRA7XX_CM_L4PER_TIMER10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028) |
| #define DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0030 |
| #define DRA7XX_CM_L4PER_TIMER11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030) |
| #define DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0038 |
| #define DRA7XX_CM_L4PER_TIMER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038) |
| #define DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0040 |
| #define DRA7XX_CM_L4PER_TIMER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040) |
| #define DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0048 |
| #define DRA7XX_CM_L4PER_TIMER4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048) |
| #define DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0050 |
| #define DRA7XX_CM_L4PER_TIMER9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050) |
| #define DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 |
| #define DRA7XX_CM_L4PER_ELM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058) |
| #define DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 |
| #define DRA7XX_CM_L4PER_GPIO2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060) |
| #define DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 |
| #define DRA7XX_CM_L4PER_GPIO3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068) |
| #define DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 |
| #define DRA7XX_CM_L4PER_GPIO4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070) |
| #define DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 |
| #define DRA7XX_CM_L4PER_GPIO5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078) |
| #define DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 |
| #define DRA7XX_CM_L4PER_GPIO6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080) |
| #define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 |
| #define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088) |
| #define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET 0x0090 |
| #define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090) |
| #define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET 0x0098 |
| #define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098) |
| #define DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 |
| #define DRA7XX_CM_L4PER_I2C1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0) |
| #define DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 |
| #define DRA7XX_CM_L4PER_I2C2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8) |
| #define DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 |
| #define DRA7XX_CM_L4PER_I2C3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0) |
| #define DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 |
| #define DRA7XX_CM_L4PER_I2C4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8) |
| #define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET 0x00c0 |
| #define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0) |
| #define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET 0x00c4 |
| #define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4) |
| #define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET 0x00c8 |
| #define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8) |
| #define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET 0x00d0 |
| #define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0) |
| #define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET 0x00d8 |
| #define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8) |
| #define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 |
| #define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0) |
| #define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 |
| #define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8) |
| #define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 |
| #define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100) |
| #define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 |
| #define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108) |
| #define DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0110 |
| #define DRA7XX_CM_L4PER_GPIO7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110) |
| #define DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0118 |
| #define DRA7XX_CM_L4PER_GPIO8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118) |
| #define DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0120 |
| #define DRA7XX_CM_L4PER_MMC3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120) |
| #define DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0128 |
| #define DRA7XX_CM_L4PER_MMC4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128) |
| #define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET 0x0130 |
| #define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130) |
| #define DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET 0x0138 |
| #define DRA7XX_CM_L4PER2_QSPI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138) |
| #define DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 |
| #define DRA7XX_CM_L4PER_UART1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140) |
| #define DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 |
| #define DRA7XX_CM_L4PER_UART2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148) |
| #define DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 |
| #define DRA7XX_CM_L4PER_UART3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150) |
| #define DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 |
| #define DRA7XX_CM_L4PER_UART4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158) |
| #define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET 0x0160 |
| #define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160) |
| #define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET 0x0168 |
| #define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168) |
| #define DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0170 |
| #define DRA7XX_CM_L4PER_UART5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170) |
| #define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET 0x0178 |
| #define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178) |
| #define DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 |
| #define DRA7XX_CM_L4SEC_STATICDEP_OFFSET 0x0184 |
| #define DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 |
| #define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET 0x0190 |
| #define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190) |
| #define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET 0x0198 |
| #define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198) |
| #define DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 |
| #define DRA7XX_CM_L4SEC_AES1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0) |
| #define DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 |
| #define DRA7XX_CM_L4SEC_AES2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8) |
| #define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 |
| #define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0) |
| #define DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x01b8 |
| #define DRA7XX_CM_L4SEC_FPKA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8) |
| #define DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 |
| #define DRA7XX_CM_L4SEC_RNG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0) |
| #define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 |
| #define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8) |
| #define DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET 0x01d0 |
| #define DRA7XX_CM_L4PER2_UART7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0) |
| #define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x01d8 |
| #define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8) |
| #define DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET 0x01e0 |
| #define DRA7XX_CM_L4PER2_UART8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0) |
| #define DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET 0x01e8 |
| #define DRA7XX_CM_L4PER2_UART9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8) |
| #define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET 0x01f0 |
| #define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0) |
| #define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET 0x01f8 |
| #define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8) |
| #define DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET 0x01fc |
| #define DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET 0x0200 |
| #define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET 0x0204 |
| #define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204) |
| #define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET 0x0208 |
| #define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208) |
| #define DRA7XX_CM_L4PER2_STATICDEP_OFFSET 0x020c |
| #define DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET 0x0210 |
| #define DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET 0x0214 |
| |
| #endif |
