// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * IPQ6018 SoC device tree source
 *
 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-ipq6018.h>
#include <dt-bindings/reset/qcom,gcc-ipq6018.h>
#include <dt-bindings/clock/qcom,apss-ipq.h>

/ {
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&intc>;

	clocks {
		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			#clock-cells = <0>;
		};

		xo: xo {
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
			#clock-cells = <0>;
		};
	};

	cpus: cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
			clock-names = "cpu";
			operating-points-v2 = <&cpu_opp_table>;
			cpu-supply = <&ipq6018_s2>;
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x1>;
			next-level-cache = <&L2_0>;
			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
			clock-names = "cpu";
			operating-points-v2 = <&cpu_opp_table>;
			cpu-supply = <&ipq6018_s2>;
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x2>;
			next-level-cache = <&L2_0>;
			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
			clock-names = "cpu";
			operating-points-v2 = <&cpu_opp_table>;
			cpu-supply = <&ipq6018_s2>;
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			enable-method = "psci";
			reg = <0x3>;
			next-level-cache = <&L2_0>;
			clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
			clock-names = "cpu";
			operating-points-v2 = <&cpu_opp_table>;
			cpu-supply = <&ipq6018_s2>;
		};

		L2_0: l2-cache {
			compatible = "cache";
			cache-level = <0x2>;
		};
	};

	cpu_opp_table: cpu_opp_table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-864000000 {
			opp-hz = /bits/ 64 <864000000>;
			opp-microvolt = <725000>;
			clock-latency-ns = <200000>;
		};
		opp-1056000000 {
			opp-hz = /bits/ 64 <1056000000>;
			opp-microvolt = <787500>;
			clock-latency-ns = <200000>;
		};
		opp-1320000000 {
			opp-hz = /bits/ 64 <1320000000>;
			opp-microvolt = <862500>;
			clock-latency-ns = <200000>;
		};
		opp-1440000000 {
			opp-hz = /bits/ 64 <1440000000>;
			opp-microvolt = <925000>;
			clock-latency-ns = <200000>;
		};
		opp-1608000000 {
			opp-hz = /bits/ 64 <1608000000>;
			opp-microvolt = <987500>;
			clock-latency-ns = <200000>;
		};
		opp-1800000000 {
			opp-hz = /bits/ 64 <1800000000>;
			opp-microvolt = <1062500>;
			clock-latency-ns = <200000>;
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm";
		};
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_regs 0 0x80>;
		#hwlock-cells = <1>;
	};

	pmuv8: pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
					 IRQ_TYPE_LEVEL_HIGH)>;
	};

	psci: psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		rpm_msg_ram: memory@0x60000 {
			reg = <0x0 0x60000 0x0 0x6000>;
			no-map;
		};

		tz: memory@4a600000 {
			reg = <0x0 0x4a600000 0x0 0x00400000>;
			no-map;
		};

		smem_region: memory@4aa00000 {
			reg = <0x0 0x4aa00000 0x0 0x00100000>;
			no-map;
		};

		q6_region: memory@4ab00000 {
			reg = <0x0 0x4ab00000 0x0 0x05500000>;
			no-map;
		};
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_region>;
		hwlocks = <&tcsr_mutex 0>;
	};

	soc: soc {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0 0 0 0 0x0 0xffffffff>;
		dma-ranges;
		compatible = "simple-bus";

		prng: qrng@e1000 {
			compatible = "qcom,prng-ee";
			reg = <0x0 0xe3000 0x0 0x1000>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		cryptobam: dma-controller@704000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x0 0x00704000 0x0 0x20000>;
			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <1>;
			qcom,controlled-remotely = <1>;
			qcom,config-pipe-trust-reg = <0>;
		};

		crypto: crypto@73a000 {
			compatible = "qcom,crypto-v5.1";
			reg = <0x0 0x0073a000 0x0 0x6000>;
			clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
				<&gcc GCC_CRYPTO_AXI_CLK>,
				<&gcc GCC_CRYPTO_CLK>;
			clock-names = "iface", "bus", "core";
			dmas = <&cryptobam 2>, <&cryptobam 3>;
			dma-names = "rx", "tx";
		};

		tlmm: pinctrl@1000000 {
			compatible = "qcom,ipq6018-pinctrl";
			reg = <0x0 0x01000000 0x0 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&tlmm 0 80>;
			interrupt-controller;
			#interrupt-cells = <2>;

			serial_3_pins: serial3-pinmux {
				pins = "gpio44", "gpio45";
				function = "blsp2_uart";
				drive-strength = <8>;
				bias-pull-down;
			};

			qpic_pins: qpic-pins {
				pins = "gpio1", "gpio3", "gpio4",
					"gpio5", "gpio6", "gpio7",
					"gpio8", "gpio10", "gpio11",
					"gpio12", "gpio13", "gpio14",
					"gpio15", "gpio17";
				function = "qpic_pad";
				drive-strength = <8>;
				bias-disable;
			};
		};

		gcc: gcc@1800000 {
			compatible = "qcom,gcc-ipq6018";
			reg = <0x0 0x01800000 0x0 0x80000>;
			clocks = <&xo>, <&sleep_clk>;
			clock-names = "xo", "sleep_clk";
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		tcsr_mutex_regs: syscon@1905000 {
			compatible = "syscon";
			reg = <0x0 0x01905000 0x0 0x8000>;
		};

		tcsr_q6: syscon@1945000 {
			compatible = "syscon";
			reg = <0x0 0x01945000 0x0 0xe000>;
		};

		blsp_dma: dma-controller@7884000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x0 0x07884000 0x0 0x2b000>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
		};

		blsp1_uart3: serial@78b1000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x0 0x078b1000 0x0 0x200>;
			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		spi_0: spi@78b5000 {
			compatible = "qcom,spi-qup-v2.2.1";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x078b5000 0x0 0x600>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			spi-max-frequency = <50000000>;
			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 12>, <&blsp_dma 13>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		spi_1: spi@78b6000 {
			compatible = "qcom,spi-qup-v2.2.1";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x078b6000 0x0 0x600>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			spi-max-frequency = <50000000>;
			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
				<&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 14>, <&blsp_dma 15>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		i2c_0: i2c@78b6000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x078b6000 0x0 0x600>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			clock-frequency  = <400000>;
			dmas = <&blsp_dma 15>, <&blsp_dma 14>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */
			compatible = "qcom,i2c-qup-v2.2.1";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x078b7000 0x0 0x600>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			clock-frequency  = <400000>;
			dmas = <&blsp_dma 17>, <&blsp_dma 16>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		qpic_bam: dma-controller@7984000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x0 0x07984000 0x0 0x1a000>;
			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_QPIC_CLK>,
				 <&gcc GCC_QPIC_AHB_CLK>;
			clock-names = "iface_clk", "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "disabled";
		};

		qpic_nand: nand@79b0000 {
			compatible = "qcom,ipq6018-nand";
			reg = <0x0 0x079b0000 0x0 0x10000>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&gcc GCC_QPIC_CLK>,
				 <&gcc GCC_QPIC_AHB_CLK>;
			clock-names = "core", "aon";

			dmas = <&qpic_bam 0>,
				<&qpic_bam 1>,
				<&qpic_bam 2>;
			dma-names = "tx", "rx", "cmd";
			pinctrl-0 = <&qpic_pins>;
			pinctrl-names = "default";
			status = "disabled";
		};

		intc: interrupt-controller@b000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <0x3>;
			reg =   <0x0 0x0b000000 0x0 0x1000>,  /*GICD*/
				<0x0 0x0b002000 0x0 0x1000>,  /*GICC*/
				<0x0 0x0b001000 0x0 0x1000>,  /*GICH*/
				<0x0 0x0b004000 0x0 0x1000>;  /*GICV*/
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
		};

		watchdog@b017000 {
			compatible = "qcom,kpss-wdt";
			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
			reg = <0x0 0x0b017000 0x0 0x40>;
			clocks = <&sleep_clk>;
			timeout-sec = <10>;
		};

		apcs_glb: mailbox@b111000 {
			compatible = "qcom,ipq6018-apcs-apps-global";
			reg = <0x0 0x0b111000 0x0 0x1000>;
			#clock-cells = <1>;
			clocks = <&a53pll>, <&xo>;
			clock-names = "pll", "xo";
			#mbox-cells = <1>;
		};

		a53pll: clock@b116000 {
			compatible = "qcom,ipq6018-a53pll";
			reg = <0x0 0x0b116000 0x0 0x40>;
			#clock-cells = <0>;
			clocks = <&xo>;
			clock-names = "xo";
		};

		timer {
			compatible = "arm,armv8-timer";
			interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
				     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
				     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
				     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
		};

		timer@b120000 {
			#address-cells = <2>;
			#size-cells = <2>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x0 0x0b120000 0x0 0x1000>;
			clock-frequency = <19200000>;

			frame@b120000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x0b121000 0x0 0x1000>,
				      <0x0 0x0b122000 0x0 0x1000>;
			};

			frame@b123000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0xb123000 0x0 0x1000>;
				status = "disabled";
			};

			frame@b124000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x0b124000 0x0 0x1000>;
				status = "disabled";
			};

			frame@b125000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x0b125000 0x0 0x1000>;
				status = "disabled";
			};

			frame@b126000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x0b126000 0x0 0x1000>;
				status = "disabled";
			};

			frame@b127000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x0b127000 0x0 0x1000>;
				status = "disabled";
			};

			frame@b128000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0 0x0b128000 0x0 0x1000>;
				status = "disabled";
			};
		};

		q6v5_wcss: remoteproc@cd00000 {
			compatible = "qcom,ipq8074-wcss-pil";
			reg = <0x0 0x0cd00000 0x0 0x4040>,
			      <0x0 0x004ab000 0x0 0x20>;
			reg-names = "qdsp6",
				    "rmb";
			interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
					      <&wcss_smp2p_in 0 0>,
					      <&wcss_smp2p_in 1 0>,
					      <&wcss_smp2p_in 2 0>,
					      <&wcss_smp2p_in 3 0>;
			interrupt-names = "wdog",
					  "fatal",
					  "ready",
					  "handover",
					  "stop-ack";

			resets = <&gcc GCC_WCSSAON_RESET>,
				 <&gcc GCC_WCSS_BCR>,
				 <&gcc GCC_WCSS_Q6_BCR>;

			reset-names = "wcss_aon_reset",
				      "wcss_reset",
				      "wcss_q6_reset";

			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "prng";

			qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;

			qcom,smem-states = <&wcss_smp2p_out 0>,
					   <&wcss_smp2p_out 1>;
			qcom,smem-state-names = "shutdown",
						"stop";

			memory-region = <&q6_region>;

			glink-edge {
				interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
				qcom,remote-pid = <1>;
				mboxes = <&apcs_glb 8>;

				qrtr_requests {
					qcom,glink-channels = "IPCRTR";
				};
			};
		};

	};

	wcss: wcss-smp2p {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;

		interrupt-parent = <&intc>;
		interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>;

		mboxes = <&apcs_glb 9>;

		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		wcss_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		wcss_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	rpm-glink {
		compatible = "qcom,glink-rpm";
		interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;
		mboxes = <&apcs_glb 0>;

		rpm_requests: glink-channel {
			compatible = "qcom,rpm-ipq6018";
			qcom,glink-channels = "rpm_requests";

			regulators {
				compatible = "qcom,rpm-mp5496-regulators";

				ipq6018_s2: s2 {
					regulator-min-microvolt = <725000>;
					regulator-max-microvolt = <1062500>;
					regulator-always-on;
				};
			};
		};
	};
};