arch/arm64/boot/dts/freescale/s32g2.dtsi

// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
 * NXP S32G2 SoC family
 *
 * Copyright (c) 2021 SUSE LLC
 * Copyright 2017-2021, 2024 NXP
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "nxp,s32g2";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	reserved-memory  {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		scmi_buf: shm@d0000000 {
			compatible = "arm,scmi-shmem";
			reg = <0x0 0xd0000000 0x0 0x80>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x0>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x1>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0x101>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cluster0_l2: l2-cache0 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};

		cluster1_l2: l2-cache1 {
			compatible = "cache";
			cache-level = <2>;
			cache-unified;
		};
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	firmware {
		scmi {
			compatible = "arm,scmi-smc";
			arm,smc-id = <0xc20000fe>;
			#address-cells = <1>;
			#size-cells = <0>;
			shmem = <&scmi_buf>;

			clks: protocol@14 {
				reg = <0x14>;
				#clock-cells = <1>;
			};
		};

		psci {
			compatible = "arm,psci-1.0";
			method = "smc";
		};
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0x80000000>;

		uart0: serial@401c8000 {
			compatible = "nxp,s32g2-linflexuart",
				     "fsl,s32v234-linflexuart";
			reg = <0x401c8000 0x3000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
			status = "disabled";
		};

		uart1: serial@401cc000 {
			compatible = "nxp,s32g2-linflexuart",
				     "fsl,s32v234-linflexuart";
			reg = <0x401cc000 0x3000>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
			status = "disabled";
		};

		uart2: serial@402bc000 {
			compatible = "nxp,s32g2-linflexuart",
				     "fsl,s32v234-linflexuart";
			reg = <0x402bc000 0x3000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
			status = "disabled";
		};

		usdhc0: mmc@402f0000 {
			compatible = "nxp,s32g2-usdhc";
			reg = <0x402f0000 0x1000>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clks 32>, <&clks 31>, <&clks 33>;
			clock-names = "ipg", "ahb", "per";
			bus-width = <8>;
			status = "disabled";
		};

		gic: interrupt-controller@50800000 {
			compatible = "arm,gic-v3";
			reg = <0x50800000 0x10000>,
			      <0x50880000 0x80000>,
			      <0x50400000 0x2000>,
			      <0x50410000 0x2000>,
			      <0x50420000 0x2000>;
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};
	};
};