// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/Five SoC
 *
 * Copyright (C) 2022 Renesas Electronics Corp.
 */

#include <dt-bindings/interrupt-controller/irq.h>

#define SOC_PERIPHERAL_IRQ(nr)	(nr + 32)

#include <arm64/renesas/r9a07g043.dtsi>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		timebase-frequency = <12000000>;

		cpu0: cpu@0 {
			compatible = "andestech,ax45mp", "riscv";
			device_type = "cpu";
			#cooling-cells = <2>;
			reg = <0x0>;
			status = "okay";
			riscv,isa = "rv64imafdc";
			riscv,isa-base = "rv64i";
			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
					       "zicntr", "zicsr", "zifencei",
					       "zihpm", "xandespmu";
			mmu-type = "riscv,sv39";
			i-cache-size = <0x8000>;
			i-cache-line-size = <0x40>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <0x40>;
			next-level-cache = <&l2cache>;
			clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
			operating-points-v2 = <&cluster0_opp>;

			cpu0_intc: interrupt-controller {
				#interrupt-cells = <1>;
				compatible = "andestech,cpu-intc", "riscv,cpu-intc";
				interrupt-controller;
			};
		};
	};
};

&pinctrl {
	gpio-ranges = <&pinctrl 0 0 232>;
};

&soc {
	dma-noncoherent;
	interrupt-parent = <&plic>;

	irqc: interrupt-controller@110a0000 {
		compatible = "renesas,r9a07g043f-irqc";
		reg = <0 0x110a0000 0 0x20000>;
		#interrupt-cells = <2>;
		#address-cells = <0>;
		interrupt-controller;
		interrupts = <32 IRQ_TYPE_LEVEL_HIGH>,
			     <33 IRQ_TYPE_LEVEL_HIGH>,
			     <34 IRQ_TYPE_LEVEL_HIGH>,
			     <35 IRQ_TYPE_LEVEL_HIGH>,
			     <36 IRQ_TYPE_LEVEL_HIGH>,
			     <37 IRQ_TYPE_LEVEL_HIGH>,
			     <38 IRQ_TYPE_LEVEL_HIGH>,
			     <39 IRQ_TYPE_LEVEL_HIGH>,
			     <40 IRQ_TYPE_LEVEL_HIGH>,
			     <476 IRQ_TYPE_LEVEL_HIGH>,
			     <477 IRQ_TYPE_LEVEL_HIGH>,
			     <478 IRQ_TYPE_LEVEL_HIGH>,
			     <479 IRQ_TYPE_LEVEL_HIGH>,
			     <480 IRQ_TYPE_LEVEL_HIGH>,
			     <481 IRQ_TYPE_LEVEL_HIGH>,
			     <482 IRQ_TYPE_LEVEL_HIGH>,
			     <483 IRQ_TYPE_LEVEL_HIGH>,
			     <484 IRQ_TYPE_LEVEL_HIGH>,
			     <485 IRQ_TYPE_LEVEL_HIGH>,
			     <486 IRQ_TYPE_LEVEL_HIGH>,
			     <487 IRQ_TYPE_LEVEL_HIGH>,
			     <488 IRQ_TYPE_LEVEL_HIGH>,
			     <489 IRQ_TYPE_LEVEL_HIGH>,
			     <490 IRQ_TYPE_LEVEL_HIGH>,
			     <491 IRQ_TYPE_LEVEL_HIGH>,
			     <492 IRQ_TYPE_LEVEL_HIGH>,
			     <493 IRQ_TYPE_LEVEL_HIGH>,
			     <494 IRQ_TYPE_LEVEL_HIGH>,
			     <495 IRQ_TYPE_LEVEL_HIGH>,
			     <496 IRQ_TYPE_LEVEL_HIGH>,
			     <497 IRQ_TYPE_LEVEL_HIGH>,
			     <498 IRQ_TYPE_LEVEL_HIGH>,
			     <499 IRQ_TYPE_LEVEL_HIGH>,
			     <500 IRQ_TYPE_LEVEL_HIGH>,
			     <501 IRQ_TYPE_LEVEL_HIGH>,
			     <502 IRQ_TYPE_LEVEL_HIGH>,
			     <503 IRQ_TYPE_LEVEL_HIGH>,
			     <504 IRQ_TYPE_LEVEL_HIGH>,
			     <505 IRQ_TYPE_LEVEL_HIGH>,
			     <506 IRQ_TYPE_LEVEL_HIGH>,
			     <507 IRQ_TYPE_LEVEL_HIGH>,
			     <57 IRQ_TYPE_LEVEL_HIGH>,
			     <66 IRQ_TYPE_EDGE_RISING>,
			     <67 IRQ_TYPE_EDGE_RISING>,
			     <68 IRQ_TYPE_EDGE_RISING>,
			     <69 IRQ_TYPE_EDGE_RISING>,
			     <70 IRQ_TYPE_EDGE_RISING>,
			     <71 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "nmi",
				  "irq0", "irq1", "irq2", "irq3",
				  "irq4", "irq5", "irq6", "irq7",
				  "tint0", "tint1", "tint2", "tint3",
				  "tint4", "tint5", "tint6", "tint7",
				  "tint8", "tint9", "tint10", "tint11",
				  "tint12", "tint13", "tint14", "tint15",
				  "tint16", "tint17", "tint18", "tint19",
				  "tint20", "tint21", "tint22", "tint23",
				  "tint24", "tint25", "tint26", "tint27",
				  "tint28", "tint29", "tint30", "tint31",
				  "bus-err", "ec7tie1-0", "ec7tie2-0",
				  "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
				  "ec7tiovf-1";
		clocks = <&cpg CPG_MOD R9A07G043_IAX45_CLK>,
			 <&cpg CPG_MOD R9A07G043_IAX45_PCLK>;
		clock-names = "clk", "pclk";
		power-domains = <&cpg>;
		resets = <&cpg R9A07G043_IAX45_RESETN>;
	};

	plic: interrupt-controller@12c00000 {
		compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
		#interrupt-cells = <2>;
		#address-cells = <0>;
		riscv,ndev = <511>;
		interrupt-controller;
		reg = <0x0 0x12c00000 0 0x400000>;
		clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>;
		power-domains = <&cpg>;
		resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
		interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
	};

	l2cache: cache-controller@13400000 {
		compatible = "andestech,ax45mp-cache", "cache";
		reg = <0x0 0x13400000 0x0 0x100000>;
		interrupts = <SOC_PERIPHERAL_IRQ(476) IRQ_TYPE_LEVEL_HIGH>;
		cache-size = <0x40000>;
		cache-line-size = <64>;
		cache-sets = <1024>;
		cache-unified;
		cache-level = <2>;
	};
};