/*
 * Copyright 2022 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 */
#ifndef _mmhub_3_0_1_SH_MASK_HEADER
#define _mmhub_3_0_1_SH_MASK_HEADER


// addressBlock: mmhub_dagbdec
//DAGB0_RDCLI0
#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI0__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI0__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI0__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI0__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI0__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI0__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI0__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI0__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI0__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI0__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI1
#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI1__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI1__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI1__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI1__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI1__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI1__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI1__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI1__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI1__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI1__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI2
#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI2__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI2__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI2__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI2__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI2__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI2__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI2__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI2__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI2__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI2__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI3
#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI3__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI3__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI3__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI3__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI3__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI3__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI3__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI3__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI3__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI3__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI4
#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI4__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI4__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI4__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI4__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI4__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI4__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI4__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI4__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI4__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI4__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI5
#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI5__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI5__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI5__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI5__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI5__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI5__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI5__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI5__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI5__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI5__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI6
#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI6__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI6__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI6__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI6__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI6__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI6__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI6__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI6__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI6__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI6__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI7
#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI7__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI7__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI7__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI7__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI7__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI7__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI7__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI7__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI7__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI7__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI8
#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI8__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI8__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI8__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI8__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI8__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI8__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI8__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI8__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI8__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI8__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI9
#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_RDCLI9__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_RDCLI9__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_RDCLI9__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_RDCLI9__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_RDCLI9__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_RDCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_RDCLI9__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_RDCLI9__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_RDCLI9__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_RDCLI9__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_RDCLI9__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_RDCLI10
#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI10__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI10__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI10__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI10__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI10__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI10__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI10__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI10__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI10__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI10__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI11
#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI11__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI11__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI11__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI11__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI11__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI11__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI11__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI11__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI11__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI11__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI12
#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI12__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI12__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI12__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI12__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI12__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI12__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI12__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI12__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI12__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI12__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI13
#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI13__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI13__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI13__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI13__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI13__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI13__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI13__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI13__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI13__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI13__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI14
#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI14__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI14__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI14__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI14__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI14__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI14__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI14__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI14__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI14__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI14__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI15
#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI15__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI15__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI15__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI15__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI15__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI15__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI15__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI15__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI15__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI15__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI16
#define DAGB0_RDCLI16__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI16__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI16__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI16__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI16__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI16__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI16__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI16__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI16__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI16__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI16__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI16__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI17
#define DAGB0_RDCLI17__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI17__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI17__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI17__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI17__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI17__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI17__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI17__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI17__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI17__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI17__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI17__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI18
#define DAGB0_RDCLI18__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI18__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI18__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI18__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI18__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI18__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI18__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI18__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI18__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI18__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI18__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI18__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI19
#define DAGB0_RDCLI19__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI19__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI19__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI19__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI19__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI19__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI19__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI19__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI19__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI19__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI19__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI19__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI20
#define DAGB0_RDCLI20__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI20__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI20__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI20__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI20__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI20__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI20__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI20__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI20__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI20__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI20__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI20__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI21
#define DAGB0_RDCLI21__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI21__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI21__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI21__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI21__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI21__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI21__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI21__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI21__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI21__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI21__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI21__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI22
#define DAGB0_RDCLI22__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI22__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI22__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI22__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI22__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI22__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI22__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI22__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI22__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI22__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI22__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI22__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI23
#define DAGB0_RDCLI23__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI23__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI23__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI23__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI23__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI23__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI23__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI23__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI23__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI23__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI23__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI23__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI24
#define DAGB0_RDCLI24__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI24__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI24__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI24__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI24__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI24__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI24__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI24__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI24__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI24__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI24__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI24__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI24__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI24__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI24__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI24__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI24__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI24__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI24__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI24__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI25
#define DAGB0_RDCLI25__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI25__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI25__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI25__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI25__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI25__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI25__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI25__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI25__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI25__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI25__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI25__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI25__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI25__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI25__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI25__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI25__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI25__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI25__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI25__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI26
#define DAGB0_RDCLI26__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI26__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI26__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI26__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI26__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI26__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI26__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI26__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI26__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI26__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI26__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI26__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI26__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI26__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI26__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI26__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI26__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI26__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI26__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI26__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI27
#define DAGB0_RDCLI27__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI27__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI27__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI27__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI27__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI27__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI27__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI27__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI27__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI27__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI27__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI27__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI27__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI27__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI27__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI27__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI27__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI27__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI27__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI27__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI28
#define DAGB0_RDCLI28__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI28__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI28__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI28__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI28__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI28__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI28__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI28__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI28__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI28__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI28__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI28__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI28__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI28__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI28__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI28__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI28__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI28__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI28__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI28__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RDCLI29
#define DAGB0_RDCLI29__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_RDCLI29__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_RDCLI29__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_RDCLI29__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_RDCLI29__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_RDCLI29__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_RDCLI29__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_RDCLI29__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_RDCLI29__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_RDCLI29__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_RDCLI29__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_RDCLI29__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_RDCLI29__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_RDCLI29__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_RDCLI29__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_RDCLI29__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_RDCLI29__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_RDCLI29__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_RDCLI29__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_RDCLI29__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_RD_CNTL
#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x0
#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0x6
#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT                                                                    0xc
#define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN__SHIFT                                                                0xf
#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x0000003FL
#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x00000FC0L
#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK                                                                      0x00007000L
#define DAGB0_RD_CNTL__VC_ROUNDROBIN_EN_MASK                                                                  0x00008000L
//DAGB0_RD_IO_CNTL
#define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE__SHIFT                                                             0x0
#define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT                                                           0x1
#define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT                                                          0x4
#define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE__SHIFT                                                             0x9
#define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT                                                           0xa
#define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT                                                          0xd
#define DAGB0_RD_IO_CNTL__COMMON_PRIORITY__SHIFT                                                              0x12
#define DAGB0_RD_IO_CNTL__OVERRIDE0_ENABLE_MASK                                                               0x00000001L
#define DAGB0_RD_IO_CNTL__OVERRIDE0_PRIORITY_MASK                                                             0x0000000EL
#define DAGB0_RD_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK                                                            0x000001F0L
#define DAGB0_RD_IO_CNTL__OVERRIDE1_ENABLE_MASK                                                               0x00000200L
#define DAGB0_RD_IO_CNTL__OVERRIDE1_PRIORITY_MASK                                                             0x00001C00L
#define DAGB0_RD_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK                                                            0x0003E000L
#define DAGB0_RD_IO_CNTL__COMMON_PRIORITY_MASK                                                                0x001C0000L
//DAGB0_RD_GMI_CNTL
#define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT                                                            0x0
#define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT                                                          0x1
#define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT                                                         0x4
#define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT                                                            0x9
#define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT                                                          0xa
#define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT                                                         0xd
#define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY__SHIFT                                                             0x12
#define DAGB0_RD_GMI_CNTL__OVERRIDE0_ENABLE_MASK                                                              0x00000001L
#define DAGB0_RD_GMI_CNTL__OVERRIDE0_PRIORITY_MASK                                                            0x0000000EL
#define DAGB0_RD_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK                                                           0x000001F0L
#define DAGB0_RD_GMI_CNTL__OVERRIDE1_ENABLE_MASK                                                              0x00000200L
#define DAGB0_RD_GMI_CNTL__OVERRIDE1_PRIORITY_MASK                                                            0x00001C00L
#define DAGB0_RD_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK                                                           0x0003E000L
#define DAGB0_RD_GMI_CNTL__COMMON_PRIORITY_MASK                                                               0x001C0000L
//DAGB0_RD_ADDR_DAGB
#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
#define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
//DAGB0_RD_CGTT_CLK_CTRL
#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x5
#define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT                                                   0xd
#define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT                                                             0x1e
#define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT                                                          0x1f
#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000001FL
#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00001FE0L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK                                                     0x1FFFE000L
#define DAGB0_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK                                                               0x40000000L
#define DAGB0_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK                                                            0x80000000L
//DAGB0_L1TLB_RD_CGTT_CLK_CTRL
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x5
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT                                             0xd
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE__SHIFT                                                       0x1e
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT                                                    0x1f
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000001FL
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00001FE0L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK                                               0x1FFFE000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_DISABLE_MASK                                                         0x40000000L
#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK                                                      0x80000000L
//DAGB0_RD_ADDR_DAGB_MAX_BURST0
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB0_RD_ADDR_DAGB_MAX_BURST1
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB0_RD_ADDR_DAGB_MAX_BURST2
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT                                                        0x0
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT                                                        0x4
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT                                                        0x8
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT                                                        0xc
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT                                                        0x10
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT                                                        0x14
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT                                                        0x18
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT                                                        0x1c
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK                                                          0x0000000FL
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK                                                          0x000000F0L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK                                                          0x00000F00L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK                                                          0x0000F000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK                                                          0x000F0000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK                                                          0x00F00000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK                                                          0x0F000000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK                                                          0xF0000000L
//DAGB0_RD_ADDR_DAGB_LAZY_TIMER2
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT                                                       0x0
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT                                                       0x4
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT                                                       0x8
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT                                                       0xc
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT                                                       0x10
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT                                                       0x14
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT                                                       0x18
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT                                                       0x1c
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK                                                         0x0000000FL
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK                                                         0x000000F0L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK                                                         0x00000F00L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK                                                         0x0000F000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK                                                         0x000F0000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK                                                         0x00F00000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK                                                         0x0F000000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK                                                         0xF0000000L
//DAGB0_RD_ADDR_DAGB_MAX_BURST3
#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT                                                        0x0
#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT                                                        0x4
#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT                                                        0x8
#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT                                                        0xc
#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT                                                        0x10
#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT                                                        0x14
#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT                                                        0x18
#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT                                                        0x1c
#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK                                                          0x0000000FL
#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK                                                          0x000000F0L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK                                                          0x00000F00L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK                                                          0x0000F000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK                                                          0x000F0000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK                                                          0x00F00000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK                                                          0x0F000000L
#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK                                                          0xF0000000L
//DAGB0_RD_ADDR_DAGB_LAZY_TIMER3
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT                                                       0x0
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT                                                       0x4
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT                                                       0x8
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT                                                       0xc
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT                                                       0x10
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT                                                       0x14
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT                                                       0x18
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT                                                       0x1c
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK                                                         0x0000000FL
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK                                                         0x000000F0L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK                                                         0x00000F00L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK                                                         0x0000F000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK                                                         0x000F0000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK                                                         0x00F00000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK                                                         0x0F000000L
#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK                                                         0xF0000000L
//DAGB0_RD_VC0_CNTL
#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_RD_VC1_CNTL
#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_RD_VC2_CNTL
#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_RD_VC3_CNTL
#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_RD_VC4_CNTL
#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_RD_VC5_CNTL
#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_RD_IO_VC_CNTL
#define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT                                                             0x0
#define DAGB0_RD_IO_VC_CNTL__MAX_BW__SHIFT                                                                    0xc
#define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT                                                             0x14
#define DAGB0_RD_IO_VC_CNTL__MIN_BW__SHIFT                                                                    0x15
#define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                        0x18
#define DAGB0_RD_IO_VC_CNTL__MAX_OSD__SHIFT                                                                   0x19
#define DAGB0_RD_IO_VC_CNTL__MAX_BW_ENABLE_MASK                                                               0x00000001L
#define DAGB0_RD_IO_VC_CNTL__MAX_BW_MASK                                                                      0x000FF000L
#define DAGB0_RD_IO_VC_CNTL__MIN_BW_ENABLE_MASK                                                               0x00100000L
#define DAGB0_RD_IO_VC_CNTL__MIN_BW_MASK                                                                      0x00E00000L
#define DAGB0_RD_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK                                                          0x01000000L
#define DAGB0_RD_IO_VC_CNTL__MAX_OSD_MASK                                                                     0xFE000000L
//DAGB0_RD_GMI_VC_CNTL
#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT                                                            0x0
#define DAGB0_RD_GMI_VC_CNTL__MAX_BW__SHIFT                                                                   0xc
#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT                                                            0x14
#define DAGB0_RD_GMI_VC_CNTL__MIN_BW__SHIFT                                                                   0x15
#define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                       0x18
#define DAGB0_RD_GMI_VC_CNTL__MAX_OSD__SHIFT                                                                  0x19
#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_ENABLE_MASK                                                              0x00000001L
#define DAGB0_RD_GMI_VC_CNTL__MAX_BW_MASK                                                                     0x000FF000L
#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_ENABLE_MASK                                                              0x00100000L
#define DAGB0_RD_GMI_VC_CNTL__MIN_BW_MASK                                                                     0x00E00000L
#define DAGB0_RD_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK                                                         0x01000000L
#define DAGB0_RD_GMI_VC_CNTL__MAX_OSD_MASK                                                                    0xFE000000L
//DAGB0_RD_CNTL_MISC
#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
#define DAGB0_RD_CNTL_MISC__UTCL2_VCI__SHIFT                                                                  0x6
#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
#define DAGB0_RD_CNTL_MISC__UTCL2_VCI_MASK                                                                    0x000001C0L
//DAGB0_RD_TLB_CREDIT
#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
#define DAGB0_RD_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
#define DAGB0_RD_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
#define DAGB0_RD_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
#define DAGB0_RD_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
#define DAGB0_RD_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
#define DAGB0_RD_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
//DAGB0_RDCLI_ASK_PENDING
#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB0_RDCLI_GO_PENDING
#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
//DAGB0_RDCLI_GBLSEND_PENDING
#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB0_RDCLI_TLB_PENDING
#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB0_RDCLI_OARB_PENDING
#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
//DAGB0_RDCLI_ASK2ARB_PENDING
#define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB0_RDCLI_ASK2ARB_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB0_RDCLI_ASK2DF_PENDING
#define DAGB0_RDCLI_ASK2DF_PENDING__BUSY__SHIFT                                                               0x0
#define DAGB0_RDCLI_ASK2DF_PENDING__BUSY_MASK                                                                 0xFFFFFFFFL
//DAGB0_RDCLI_OSD_PENDING
#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB0_RDCLI_ASK_OSD_PENDING
#define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB0_RDCLI_ASK_OSD_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB0_WRCLI0
#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI0__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI0__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI0__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI0__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI0__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI0__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI0__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI0__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI0__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI0__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI0__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI1
#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI1__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI1__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI1__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI1__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI1__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI1__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI1__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI1__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI1__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI1__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI1__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI2
#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI2__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI2__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI2__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI2__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI2__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI2__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI2__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI2__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI2__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI2__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI2__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI3
#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI3__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI3__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI3__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI3__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI3__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI3__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI3__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI3__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI3__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI3__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI3__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI4
#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI4__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI4__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI4__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI4__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI4__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI4__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI4__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI4__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI4__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI4__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI4__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI5
#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI5__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI5__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI5__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI5__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI5__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI5__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI5__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI5__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI5__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI5__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI5__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI6
#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI6__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI6__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI6__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI6__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI6__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI6__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI6__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI6__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI6__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI6__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI6__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI7
#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI7__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI7__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI7__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI7__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI7__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI7__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI7__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI7__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI7__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI7__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI7__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI8
#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI8__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI8__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI8__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI8__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI8__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI8__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI8__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI8__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI8__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI8__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI8__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI9
#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT                                                                        0x0
#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT                                                                 0x3
#define DAGB0_WRCLI9__URG_HIGH__SHIFT                                                                         0x4
#define DAGB0_WRCLI9__URG_LOW__SHIFT                                                                          0x8
#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT                                                                    0xc
#define DAGB0_WRCLI9__MAX_BW__SHIFT                                                                           0xd
#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT                                                                    0x15
#define DAGB0_WRCLI9__MIN_BW__SHIFT                                                                           0x16
#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT                                                               0x19
#define DAGB0_WRCLI9__MAX_OSD__SHIFT                                                                          0x1a
#define DAGB0_WRCLI9__VIRT_CHAN_MASK                                                                          0x00000007L
#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK                                                                   0x00000008L
#define DAGB0_WRCLI9__URG_HIGH_MASK                                                                           0x000000F0L
#define DAGB0_WRCLI9__URG_LOW_MASK                                                                            0x00000F00L
#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK                                                                      0x00001000L
#define DAGB0_WRCLI9__MAX_BW_MASK                                                                             0x001FE000L
#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK                                                                      0x00200000L
#define DAGB0_WRCLI9__MIN_BW_MASK                                                                             0x01C00000L
#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK                                                                 0x02000000L
#define DAGB0_WRCLI9__MAX_OSD_MASK                                                                            0xFC000000L
//DAGB0_WRCLI10
#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI10__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI10__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI10__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI10__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI10__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI10__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI10__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI10__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI10__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI10__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI10__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI11
#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI11__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI11__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI11__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI11__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI11__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI11__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI11__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI11__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI11__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI11__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI11__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI12
#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI12__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI12__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI12__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI12__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI12__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI12__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI12__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI12__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI12__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI12__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI12__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI13
#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI13__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI13__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI13__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI13__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI13__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI13__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI13__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI13__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI13__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI13__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI13__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI14
#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI14__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI14__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI14__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI14__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI14__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI14__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI14__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI14__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI14__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI14__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI14__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI15
#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI15__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI15__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI15__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI15__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI15__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI15__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI15__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI15__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI15__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI15__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI15__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI16
#define DAGB0_WRCLI16__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI16__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI16__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI16__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI16__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI16__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI16__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI16__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI16__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI16__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI16__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI16__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI17
#define DAGB0_WRCLI17__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI17__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI17__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI17__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI17__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI17__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI17__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI17__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI17__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI17__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI17__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI17__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI18
#define DAGB0_WRCLI18__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI18__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI18__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI18__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI18__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI18__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI18__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI18__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI18__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI18__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI18__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI18__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI19
#define DAGB0_WRCLI19__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI19__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI19__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI19__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI19__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI19__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI19__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI19__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI19__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI19__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI19__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI19__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI20
#define DAGB0_WRCLI20__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI20__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI20__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI20__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI20__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI20__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI20__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI20__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI20__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI20__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI20__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI20__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI21
#define DAGB0_WRCLI21__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI21__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI21__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI21__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI21__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI21__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI21__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI21__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI21__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI21__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI21__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI21__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI22
#define DAGB0_WRCLI22__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI22__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI22__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI22__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI22__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI22__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI22__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI22__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI22__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI22__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI22__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI22__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI23
#define DAGB0_WRCLI23__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI23__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI23__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI23__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI23__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI23__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI23__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI23__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI23__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI23__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI23__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI23__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI24
#define DAGB0_WRCLI24__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI24__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI24__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI24__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI24__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI24__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI24__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI24__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI24__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI24__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI24__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI24__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI24__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI24__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI24__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI24__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI24__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI24__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI24__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI24__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI25
#define DAGB0_WRCLI25__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI25__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI25__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI25__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI25__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI25__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI25__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI25__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI25__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI25__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI25__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI25__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI25__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI25__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI25__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI25__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI25__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI25__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI25__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI25__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI26
#define DAGB0_WRCLI26__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI26__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI26__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI26__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI26__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI26__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI26__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI26__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI26__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI26__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI26__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI26__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI26__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI26__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI26__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI26__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI26__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI26__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI26__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI26__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI27
#define DAGB0_WRCLI27__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI27__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI27__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI27__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI27__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI27__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI27__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI27__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI27__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI27__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI27__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI27__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI27__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI27__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI27__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI27__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI27__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI27__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI27__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI27__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI28
#define DAGB0_WRCLI28__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI28__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI28__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI28__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI28__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI28__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI28__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI28__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI28__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI28__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI28__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI28__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI28__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI28__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI28__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI28__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI28__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI28__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI28__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI28__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WRCLI29
#define DAGB0_WRCLI29__VIRT_CHAN__SHIFT                                                                       0x0
#define DAGB0_WRCLI29__CHECK_TLB_CREDIT__SHIFT                                                                0x3
#define DAGB0_WRCLI29__URG_HIGH__SHIFT                                                                        0x4
#define DAGB0_WRCLI29__URG_LOW__SHIFT                                                                         0x8
#define DAGB0_WRCLI29__MAX_BW_ENABLE__SHIFT                                                                   0xc
#define DAGB0_WRCLI29__MAX_BW__SHIFT                                                                          0xd
#define DAGB0_WRCLI29__MIN_BW_ENABLE__SHIFT                                                                   0x15
#define DAGB0_WRCLI29__MIN_BW__SHIFT                                                                          0x16
#define DAGB0_WRCLI29__OSD_LIMITER_ENABLE__SHIFT                                                              0x19
#define DAGB0_WRCLI29__MAX_OSD__SHIFT                                                                         0x1a
#define DAGB0_WRCLI29__VIRT_CHAN_MASK                                                                         0x00000007L
#define DAGB0_WRCLI29__CHECK_TLB_CREDIT_MASK                                                                  0x00000008L
#define DAGB0_WRCLI29__URG_HIGH_MASK                                                                          0x000000F0L
#define DAGB0_WRCLI29__URG_LOW_MASK                                                                           0x00000F00L
#define DAGB0_WRCLI29__MAX_BW_ENABLE_MASK                                                                     0x00001000L
#define DAGB0_WRCLI29__MAX_BW_MASK                                                                            0x001FE000L
#define DAGB0_WRCLI29__MIN_BW_ENABLE_MASK                                                                     0x00200000L
#define DAGB0_WRCLI29__MIN_BW_MASK                                                                            0x01C00000L
#define DAGB0_WRCLI29__OSD_LIMITER_ENABLE_MASK                                                                0x02000000L
#define DAGB0_WRCLI29__MAX_OSD_MASK                                                                           0xFC000000L
//DAGB0_WR_CNTL
#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT                                                               0x0
#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT                                                                0x6
#define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN__SHIFT                                                                0xc
#define DAGB0_WR_CNTL__UPDATE_FED__SHIFT                                                                      0xd
#define DAGB0_WR_CNTL__UPDATE_NACK__SHIFT                                                                     0xe
#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK                                                                 0x0000003FL
#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK                                                                  0x00000FC0L
#define DAGB0_WR_CNTL__VC_ROUNDROBIN_EN_MASK                                                                  0x00001000L
#define DAGB0_WR_CNTL__UPDATE_FED_MASK                                                                        0x00002000L
#define DAGB0_WR_CNTL__UPDATE_NACK_MASK                                                                       0x00004000L
//DAGB0_WR_IO_CNTL
#define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE__SHIFT                                                             0x0
#define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY__SHIFT                                                           0x1
#define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID__SHIFT                                                          0x4
#define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE__SHIFT                                                             0x9
#define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY__SHIFT                                                           0xa
#define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID__SHIFT                                                          0xd
#define DAGB0_WR_IO_CNTL__COMMON_PRIORITY__SHIFT                                                              0x12
#define DAGB0_WR_IO_CNTL__OVERRIDE0_ENABLE_MASK                                                               0x00000001L
#define DAGB0_WR_IO_CNTL__OVERRIDE0_PRIORITY_MASK                                                             0x0000000EL
#define DAGB0_WR_IO_CNTL__OVERRIDE0_CLIENT_ID_MASK                                                            0x000001F0L
#define DAGB0_WR_IO_CNTL__OVERRIDE1_ENABLE_MASK                                                               0x00000200L
#define DAGB0_WR_IO_CNTL__OVERRIDE1_PRIORITY_MASK                                                             0x00001C00L
#define DAGB0_WR_IO_CNTL__OVERRIDE1_CLIENT_ID_MASK                                                            0x0003E000L
#define DAGB0_WR_IO_CNTL__COMMON_PRIORITY_MASK                                                                0x001C0000L
//DAGB0_WR_GMI_CNTL
#define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE__SHIFT                                                            0x0
#define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY__SHIFT                                                          0x1
#define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID__SHIFT                                                         0x4
#define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE__SHIFT                                                            0x9
#define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY__SHIFT                                                          0xa
#define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID__SHIFT                                                         0xd
#define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY__SHIFT                                                             0x12
#define DAGB0_WR_GMI_CNTL__OVERRIDE0_ENABLE_MASK                                                              0x00000001L
#define DAGB0_WR_GMI_CNTL__OVERRIDE0_PRIORITY_MASK                                                            0x0000000EL
#define DAGB0_WR_GMI_CNTL__OVERRIDE0_CLIENT_ID_MASK                                                           0x000001F0L
#define DAGB0_WR_GMI_CNTL__OVERRIDE1_ENABLE_MASK                                                              0x00000200L
#define DAGB0_WR_GMI_CNTL__OVERRIDE1_PRIORITY_MASK                                                            0x00001C00L
#define DAGB0_WR_GMI_CNTL__OVERRIDE1_CLIENT_ID_MASK                                                           0x0003E000L
#define DAGB0_WR_GMI_CNTL__COMMON_PRIORITY_MASK                                                               0x001C0000L
//DAGB0_WR_ADDR_DAGB
#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT                                                                  0xd
#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK                                                                       0x00001F80L
#define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK                                                                    0x00002000L
//DAGB0_WR_CGTT_CLK_CTRL
#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                               0x0
#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                         0x5
#define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT                                                   0xd
#define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT                                                             0x1e
#define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT                                                          0x1f
#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                 0x0000001FL
#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                           0x00001FE0L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK                                                     0x1FFFE000L
#define DAGB0_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK                                                               0x40000000L
#define DAGB0_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK                                                            0x80000000L
//DAGB0_L1TLB_WR_CGTT_CLK_CTRL
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                         0x0
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                   0x5
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT                                             0xd
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE__SHIFT                                                       0x1e
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT                                                    0x1f
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK                                                           0x0000001FL
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                     0x00001FE0L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK                                               0x1FFFE000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_DISABLE_MASK                                                         0x40000000L
#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK                                                      0x80000000L
//DAGB0_WR_ADDR_DAGB_MAX_BURST0
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB0_WR_ADDR_DAGB_MAX_BURST1
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB0_WR_ADDR_DAGB_MAX_BURST2
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT                                                        0x0
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT                                                        0x4
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT                                                        0x8
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT                                                        0xc
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT                                                        0x10
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT                                                        0x14
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT                                                        0x18
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT                                                        0x1c
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK                                                          0x0000000FL
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK                                                          0x000000F0L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK                                                          0x00000F00L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK                                                          0x0000F000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK                                                          0x000F0000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK                                                          0x00F00000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK                                                          0x0F000000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK                                                          0xF0000000L
//DAGB0_WR_ADDR_DAGB_LAZY_TIMER2
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT                                                       0x0
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT                                                       0x4
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT                                                       0x8
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT                                                       0xc
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT                                                       0x10
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT                                                       0x14
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT                                                       0x18
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT                                                       0x1c
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK                                                         0x0000000FL
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK                                                         0x000000F0L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK                                                         0x00000F00L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK                                                         0x0000F000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK                                                         0x000F0000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK                                                         0x00F00000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK                                                         0x0F000000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK                                                         0xF0000000L
//DAGB0_WR_ADDR_DAGB_MAX_BURST3
#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT                                                        0x0
#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT                                                        0x4
#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT                                                        0x8
#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT                                                        0xc
#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT                                                        0x10
#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT                                                        0x14
#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT                                                        0x18
#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT                                                        0x1c
#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK                                                          0x0000000FL
#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK                                                          0x000000F0L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK                                                          0x00000F00L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK                                                          0x0000F000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK                                                          0x000F0000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK                                                          0x00F00000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK                                                          0x0F000000L
#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK                                                          0xF0000000L
//DAGB0_WR_ADDR_DAGB_LAZY_TIMER3
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT                                                       0x0
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT                                                       0x4
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT                                                       0x8
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT                                                       0xc
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT                                                       0x10
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT                                                       0x14
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT                                                       0x18
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT                                                       0x1c
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK                                                         0x0000000FL
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK                                                         0x000000F0L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK                                                         0x00000F00L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK                                                         0x0000F000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK                                                         0x000F0000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK                                                         0x00F00000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK                                                         0x0F000000L
#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK                                                         0xF0000000L
//DAGB0_WR_DATA_DAGB
#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT                                                                0x0
#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT                                                          0x3
#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT                                                          0x6
#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT                                                                     0x7
#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK                                                                  0x00000007L
#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK                                                            0x00000038L
#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK                                                            0x00000040L
#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK                                                                       0x00001F80L
//DAGB0_WR_DATA_DAGB_MAX_BURST0
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT                                                         0x0
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT                                                         0x4
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT                                                         0x8
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT                                                         0xc
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT                                                         0x10
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT                                                         0x14
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT                                                         0x18
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT                                                         0x1c
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK                                                           0x0000000FL
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK                                                           0x000000F0L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK                                                           0x00000F00L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK                                                           0x0000F000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK                                                           0x000F0000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK                                                           0x00F00000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK                                                           0x0F000000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK                                                           0xF0000000L
//DAGB0_WR_DATA_DAGB_LAZY_TIMER0
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT                                                        0x0
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT                                                        0x4
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT                                                        0x8
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT                                                        0xc
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT                                                        0x10
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT                                                        0x14
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT                                                        0x18
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT                                                        0x1c
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK                                                          0x0000000FL
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK                                                          0x000000F0L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK                                                          0x00000F00L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK                                                          0x0000F000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK                                                          0x000F0000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK                                                          0x00F00000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK                                                          0x0F000000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK                                                          0xF0000000L
//DAGB0_WR_DATA_DAGB_MAX_BURST1
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT                                                         0x0
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT                                                         0x4
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT                                                        0x8
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT                                                        0xc
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT                                                        0x10
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT                                                        0x14
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT                                                        0x18
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT                                                        0x1c
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK                                                           0x0000000FL
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK                                                           0x000000F0L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK                                                          0x00000F00L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK                                                          0x0000F000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK                                                          0x000F0000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK                                                          0x00F00000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK                                                          0x0F000000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK                                                          0xF0000000L
//DAGB0_WR_DATA_DAGB_LAZY_TIMER1
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT                                                        0x0
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT                                                        0x4
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT                                                       0x8
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT                                                       0xc
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT                                                       0x10
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT                                                       0x14
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT                                                       0x18
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT                                                       0x1c
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK                                                          0x0000000FL
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK                                                          0x000000F0L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK                                                         0x00000F00L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK                                                         0x0000F000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK                                                         0x000F0000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK                                                         0x00F00000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK                                                         0x0F000000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK                                                         0xF0000000L
//DAGB0_WR_DATA_DAGB_MAX_BURST2
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT                                                        0x0
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT                                                        0x4
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT                                                        0x8
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT                                                        0xc
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT                                                        0x10
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT                                                        0x14
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT                                                        0x18
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT                                                        0x1c
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK                                                          0x0000000FL
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK                                                          0x000000F0L
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK                                                          0x00000F00L
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK                                                          0x0000F000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK                                                          0x000F0000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK                                                          0x00F00000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK                                                          0x0F000000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK                                                          0xF0000000L
//DAGB0_WR_DATA_DAGB_LAZY_TIMER2
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT                                                       0x0
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT                                                       0x4
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT                                                       0x8
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT                                                       0xc
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT                                                       0x10
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT                                                       0x14
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT                                                       0x18
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT                                                       0x1c
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK                                                         0x0000000FL
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK                                                         0x000000F0L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK                                                         0x00000F00L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK                                                         0x0000F000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK                                                         0x000F0000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK                                                         0x00F00000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK                                                         0x0F000000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK                                                         0xF0000000L
//DAGB0_WR_DATA_DAGB_MAX_BURST3
#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24__SHIFT                                                        0x0
#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25__SHIFT                                                        0x4
#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26__SHIFT                                                        0x8
#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27__SHIFT                                                        0xc
#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28__SHIFT                                                        0x10
#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29__SHIFT                                                        0x14
#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30__SHIFT                                                        0x18
#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31__SHIFT                                                        0x1c
#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24_MASK                                                          0x0000000FL
#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25_MASK                                                          0x000000F0L
#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26_MASK                                                          0x00000F00L
#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27_MASK                                                          0x0000F000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28_MASK                                                          0x000F0000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29_MASK                                                          0x00F00000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30_MASK                                                          0x0F000000L
#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31_MASK                                                          0xF0000000L
//DAGB0_WR_DATA_DAGB_LAZY_TIMER3
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24__SHIFT                                                       0x0
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25__SHIFT                                                       0x4
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26__SHIFT                                                       0x8
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27__SHIFT                                                       0xc
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28__SHIFT                                                       0x10
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29__SHIFT                                                       0x14
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30__SHIFT                                                       0x18
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31__SHIFT                                                       0x1c
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24_MASK                                                         0x0000000FL
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25_MASK                                                         0x000000F0L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26_MASK                                                         0x00000F00L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27_MASK                                                         0x0000F000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28_MASK                                                         0x000F0000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29_MASK                                                         0x00F00000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30_MASK                                                         0x0F000000L
#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31_MASK                                                         0xF0000000L
//DAGB0_WR_VC0_CNTL
#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_WR_VC1_CNTL
#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_WR_VC2_CNTL
#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_WR_VC3_CNTL
#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_WR_VC4_CNTL
#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_WR_VC5_CNTL
#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT                                                                 0x0
#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT                                                               0xb
#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT                                                                      0xc
#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT                                                               0x14
#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT                                                                      0x15
#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                          0x18
#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT                                                                     0x19
#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK                                                                   0x0000001FL
#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK                                                                 0x00000800L
#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK                                                                        0x000FF000L
#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK                                                                 0x00100000L
#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK                                                                        0x00E00000L
#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK                                                            0x01000000L
#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK                                                                       0xFE000000L
//DAGB0_WR_IO_VC_CNTL
#define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE__SHIFT                                                             0x0
#define DAGB0_WR_IO_VC_CNTL__MAX_BW__SHIFT                                                                    0xc
#define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE__SHIFT                                                             0x14
#define DAGB0_WR_IO_VC_CNTL__MIN_BW__SHIFT                                                                    0x15
#define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                        0x18
#define DAGB0_WR_IO_VC_CNTL__MAX_OSD__SHIFT                                                                   0x19
#define DAGB0_WR_IO_VC_CNTL__MAX_BW_ENABLE_MASK                                                               0x00000001L
#define DAGB0_WR_IO_VC_CNTL__MAX_BW_MASK                                                                      0x000FF000L
#define DAGB0_WR_IO_VC_CNTL__MIN_BW_ENABLE_MASK                                                               0x00100000L
#define DAGB0_WR_IO_VC_CNTL__MIN_BW_MASK                                                                      0x00E00000L
#define DAGB0_WR_IO_VC_CNTL__OSD_LIMITER_ENABLE_MASK                                                          0x01000000L
#define DAGB0_WR_IO_VC_CNTL__MAX_OSD_MASK                                                                     0xFE000000L
//DAGB0_WR_GMI_VC_CNTL
#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE__SHIFT                                                            0x0
#define DAGB0_WR_GMI_VC_CNTL__MAX_BW__SHIFT                                                                   0xc
#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE__SHIFT                                                            0x14
#define DAGB0_WR_GMI_VC_CNTL__MIN_BW__SHIFT                                                                   0x15
#define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE__SHIFT                                                       0x18
#define DAGB0_WR_GMI_VC_CNTL__MAX_OSD__SHIFT                                                                  0x19
#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_ENABLE_MASK                                                              0x00000001L
#define DAGB0_WR_GMI_VC_CNTL__MAX_BW_MASK                                                                     0x000FF000L
#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_ENABLE_MASK                                                              0x00100000L
#define DAGB0_WR_GMI_VC_CNTL__MIN_BW_MASK                                                                     0x00E00000L
#define DAGB0_WR_GMI_VC_CNTL__OSD_LIMITER_ENABLE_MASK                                                         0x01000000L
#define DAGB0_WR_GMI_VC_CNTL__MAX_OSD_MASK                                                                    0xFE000000L
//DAGB0_WR_CNTL_MISC
#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT                                                           0x0
#define DAGB0_WR_CNTL_MISC__HDP_CID__SHIFT                                                                    0x6
#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK                                                             0x0000003FL
#define DAGB0_WR_CNTL_MISC__HDP_CID_MASK                                                                      0x000007C0L
//DAGB0_WR_TLB_CREDIT
#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT                                                                      0x0
#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT                                                                      0x5
#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT                                                                      0xa
#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT                                                                      0xf
#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT                                                                      0x14
#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT                                                                      0x19
#define DAGB0_WR_TLB_CREDIT__TLB0_MASK                                                                        0x0000001FL
#define DAGB0_WR_TLB_CREDIT__TLB1_MASK                                                                        0x000003E0L
#define DAGB0_WR_TLB_CREDIT__TLB2_MASK                                                                        0x00007C00L
#define DAGB0_WR_TLB_CREDIT__TLB3_MASK                                                                        0x000F8000L
#define DAGB0_WR_TLB_CREDIT__TLB4_MASK                                                                        0x01F00000L
#define DAGB0_WR_TLB_CREDIT__TLB5_MASK                                                                        0x3E000000L
//DAGB0_WR_DATA_CREDIT
#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT                                                         0x0
#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT                                                      0x8
#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT                                                     0x10
#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT                                                      0x18
#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK                                                           0x000000FFL
#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK                                                        0x0000FF00L
#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK                                                       0x00FF0000L
#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK                                                        0xFF000000L
//DAGB0_WR_MISC_CREDIT
#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT                                                            0x0
#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT                                                             0x6
#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK                                                              0x0000003FL
#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK                                                               0x000001C0L
//DAGB0_WR_DATA_FIFO_CREDIT_CNTL1
#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                    0x0
#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                    0x5
#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                    0xa
#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                    0xf
#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                   0x14
#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT                                                       0x19
#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT                                                        0x1a
#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0__SHIFT                                                          0x1b
#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK                                                      0x0000001FL
#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK                                                      0x000003E0L
#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK                                                      0x00007C00L
#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK                                                      0x000F8000L
#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK                                                     0x01F00000L
#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__VC_MODE_MASK                                                         0x02000000L
#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX_EQ_MASK                                                          0x04000000L
#define DAGB0_WR_DATA_FIFO_CREDIT_CNTL1__FIX0_MASK                                                            0x08000000L
//DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT                                                  0x0
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT                                                  0x5
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT                                                  0xa
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT                                                  0xf
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT                                                 0x14
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT                                                     0x1a
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT                                                      0x1b
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT                                                        0x1c
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK                                                    0x0000001FL
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK                                                    0x000003E0L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK                                                    0x00007C00L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK                                                    0x000F8000L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK                                                   0x03F00000L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK                                                       0x04000000L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK                                                        0x08000000L
#define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK                                                          0x10000000L
//DAGB0_WRCLI_ASK_PENDING
#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB0_WRCLI_GO_PENDING
#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT                                                                   0x0
#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK                                                                     0xFFFFFFFFL
//DAGB0_WRCLI_GBLSEND_PENDING
#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB0_WRCLI_TLB_PENDING
#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB0_WRCLI_OARB_PENDING
#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT                                                                 0x0
#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK                                                                   0xFFFFFFFFL
//DAGB0_WRCLI_ASK2ARB_PENDING
#define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB0_WRCLI_ASK2ARB_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB0_WRCLI_ASK2DF_PENDING
#define DAGB0_WRCLI_ASK2DF_PENDING__BUSY__SHIFT                                                               0x0
#define DAGB0_WRCLI_ASK2DF_PENDING__BUSY_MASK                                                                 0xFFFFFFFFL
//DAGB0_WRCLI_OSD_PENDING
#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT                                                                  0x0
#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK                                                                    0xFFFFFFFFL
//DAGB0_WRCLI_ASK_OSD_PENDING
#define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB0_WRCLI_ASK_OSD_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB0_WRCLI_DBUS_ASK_PENDING
#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT                                                             0x0
#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK                                                               0xFFFFFFFFL
//DAGB0_WRCLI_DBUS_GO_PENDING
#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT                                                              0x0
#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK                                                                0xFFFFFFFFL
//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE
#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT                                                         0x0
#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK                                                           0xFFFFFFFFL
//DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE
#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT                                                   0x0
#define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK                                                     0xFFFFFFFFL
//DAGB0_DAGB_DLY
#define DAGB0_DAGB_DLY__DLY__SHIFT                                                                            0x0
#define DAGB0_DAGB_DLY__CLI__SHIFT                                                                            0x8
#define DAGB0_DAGB_DLY__POS__SHIFT                                                                            0x10
#define DAGB0_DAGB_DLY__DLY_MASK                                                                              0x000000FFL
#define DAGB0_DAGB_DLY__CLI_MASK                                                                              0x0000FF00L
#define DAGB0_DAGB_DLY__POS_MASK                                                                              0x000F0000L
//DAGB0_CNTL_MISC
#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT                                                                 0x0
#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK                                                                   0x0000003FL
//DAGB0_CNTL_MISC2
#define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE__SHIFT                                                             0x0
#define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE__SHIFT                                                             0x1
#define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE__SHIFT                                                          0x2
#define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE__SHIFT                                                          0x3
#define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE__SHIFT                                                            0x4
#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT                                                                     0x5
#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK__SHIFT                                                          0x6
#define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK__SHIFT                                                      0x7
#define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS__SHIFT                                                       0x8
#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT                                                              0x9
#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG__SHIFT                                                 0xa
#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG__SHIFT                                                 0xb
#define DAGB0_CNTL_MISC2__WR_BUSY_OVERRIDE_MASK                                                               0x00000001L
#define DAGB0_CNTL_MISC2__RD_BUSY_OVERRIDE_MASK                                                               0x00000002L
#define DAGB0_CNTL_MISC2__TLBWR_BUSY_OVERRIDE_MASK                                                            0x00000004L
#define DAGB0_CNTL_MISC2__TLBRD_BUSY_OVERRIDE_MASK                                                            0x00000008L
#define DAGB0_CNTL_MISC2__SDP_BUSY_OVERRIDE_MASK                                                              0x00000010L
#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK                                                                       0x00000020L
#define DAGB0_CNTL_MISC2__ENABLE_PARITY_CHECK_MASK                                                            0x00000040L
#define DAGB0_CNTL_MISC2__RDATA_PARITY_CHECK4NACK_MASK                                                        0x00000080L
#define DAGB0_CNTL_MISC2__WDATA_PARITY_CHECK4RAS_MASK                                                         0x00000100L
#define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK                                                                0x00000200L
#define DAGB0_CNTL_MISC2__DISABLE_RDRET_TAP_CHAIN_FGCG_MASK                                                   0x00000400L
#define DAGB0_CNTL_MISC2__DISABLE_WRRET_TAP_CHAIN_FGCG_MASK                                                   0x00000800L
//DAGB0_FIFO_EMPTY
#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT                                                                        0x0
#define DAGB0_FIFO_EMPTY__EMPTY_MASK                                                                          0x0001FFFFL
//DAGB0_FIFO_FULL
#define DAGB0_FIFO_FULL__FULL__SHIFT                                                                          0x0
#define DAGB0_FIFO_FULL__FULL_MASK                                                                            0x0000FFFFL
//DAGB0_RD_CREDITS_FULL
#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT                                                                    0x0
#define DAGB0_RD_CREDITS_FULL__FULL_MASK                                                                      0x0000007FL
//DAGB0_WR_CREDITS_FULL
#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT                                                                    0x0
#define DAGB0_WR_CREDITS_FULL__FULL_MASK                                                                      0x0001FFFFL
//DAGB0_PERFCOUNTER_LO
#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                               0x0
#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                 0xFFFFFFFFL
//DAGB0_PERFCOUNTER_HI
#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                               0x0
#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                            0x10
#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                 0x0000FFFFL
#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                              0xFFFF0000L
//DAGB0_PERFCOUNTER0_CFG
#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB0_PERFCOUNTER1_CFG
#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB0_PERFCOUNTER2_CFG
#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                               0x0
#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                           0x8
#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                              0x18
#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                                 0x1c
#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                  0x1d
#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                                 0x000000FFL
#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                             0x0000FF00L
#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                                0x0F000000L
#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK                                                                   0x10000000L
#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK                                                                    0x20000000L
//DAGB0_PERFCOUNTER_RSLT_CNTL
#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                               0x0
#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                     0x8
#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                      0x10
#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                        0x18
#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                         0x19
#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                              0x1a
#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                 0x00000003L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                       0x0000FF00L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                        0x00FF0000L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                          0x01000000L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                           0x02000000L
#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                0x04000000L
//DAGB0_L1TLB_REG_RW
#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT                                                       0x0
#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT                                                        0x1
#define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT                                                                    0x2
#define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK                                                         0x00000001L
#define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK                                                          0x00000002L
#define DAGB0_L1TLB_REG_RW__RESERVE_MASK                                                                      0x3FFFFFFCL
//DAGB0_RESERVE1
#define DAGB0_RESERVE1__RESERVE__SHIFT                                                                        0x0
#define DAGB0_RESERVE1__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB0_RESERVE2
#define DAGB0_RESERVE2__RESERVE__SHIFT                                                                        0x0
#define DAGB0_RESERVE2__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB0_RESERVE3
#define DAGB0_RESERVE3__RESERVE__SHIFT                                                                        0x0
#define DAGB0_RESERVE3__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB0_RESERVE4
#define DAGB0_RESERVE4__RESERVE__SHIFT                                                                        0x0
#define DAGB0_RESERVE4__RESERVE_MASK                                                                          0xFFFFFFFFL
//DAGB0_SDP_RD_BW_CNTL
#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE__SHIFT                                                            0x0
#define DAGB0_SDP_RD_BW_CNTL__MAX_BW__SHIFT                                                                   0x1
#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE__SHIFT                                                            0x9
#define DAGB0_SDP_RD_BW_CNTL__MIN_BW__SHIFT                                                                   0xa
#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW__SHIFT                                                            0xd
#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_ENABLE_MASK                                                              0x00000001L
#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_MASK                                                                     0x000001FEL
#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_ENABLE_MASK                                                              0x00000200L
#define DAGB0_SDP_RD_BW_CNTL__MIN_BW_MASK                                                                     0x00001C00L
#define DAGB0_SDP_RD_BW_CNTL__MAX_BW_WINDOW_MASK                                                              0x0007E000L
//DAGB0_SDP_PRIORITY_OVERRIDE
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY__SHIFT                                                0x0
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID__SHIFT                                               0x4
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD__SHIFT                                          0x9
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR__SHIFT                                          0xa
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD__SHIFT                                           0xb
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR__SHIFT                                           0xc
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD__SHIFT                                            0xd
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR__SHIFT                                            0xe
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY__SHIFT                                                0x10
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID__SHIFT                                               0x14
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD__SHIFT                                          0x19
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR__SHIFT                                          0x1a
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD__SHIFT                                           0x1b
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR__SHIFT                                           0x1c
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD__SHIFT                                            0x1d
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR__SHIFT                                            0x1e
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_PRIORITY_MASK                                                  0x0000000FL
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_CLIENT_ID_MASK                                                 0x000001F0L
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_RD_MASK                                            0x00000200L
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_DRAM_WR_MASK                                            0x00000400L
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_RD_MASK                                             0x00000800L
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_GMI_WR_MASK                                             0x00001000L
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_RD_MASK                                              0x00002000L
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE0_ENABLE_IO_WR_MASK                                              0x00004000L
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_PRIORITY_MASK                                                  0x000F0000L
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_CLIENT_ID_MASK                                                 0x01F00000L
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_RD_MASK                                            0x02000000L
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_DRAM_WR_MASK                                            0x04000000L
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_RD_MASK                                             0x08000000L
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_GMI_WR_MASK                                             0x10000000L
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_RD_MASK                                              0x20000000L
#define DAGB0_SDP_PRIORITY_OVERRIDE__OVERRIDE1_ENABLE_IO_WR_MASK                                              0x40000000L
//DAGB0_SDP_RD_PRIORITY
#define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY__SHIFT                                                         0x0
#define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY__SHIFT                                                         0x4
#define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY__SHIFT                                                         0x8
#define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY__SHIFT                                                         0xc
#define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY__SHIFT                                                         0x10
#define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY__SHIFT                                                         0x14
#define DAGB0_SDP_RD_PRIORITY__RD_VC0_PRIORITY_MASK                                                           0x0000000FL
#define DAGB0_SDP_RD_PRIORITY__RD_VC1_PRIORITY_MASK                                                           0x000000F0L
#define DAGB0_SDP_RD_PRIORITY__RD_VC2_PRIORITY_MASK                                                           0x00000F00L
#define DAGB0_SDP_RD_PRIORITY__RD_VC3_PRIORITY_MASK                                                           0x0000F000L
#define DAGB0_SDP_RD_PRIORITY__RD_VC4_PRIORITY_MASK                                                           0x000F0000L
#define DAGB0_SDP_RD_PRIORITY__RD_VC5_PRIORITY_MASK                                                           0x00F00000L
//DAGB0_SDP_WR_PRIORITY
#define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY__SHIFT                                                         0x0
#define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY__SHIFT                                                         0x4
#define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY__SHIFT                                                         0x8
#define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY__SHIFT                                                         0xc
#define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY__SHIFT                                                         0x10
#define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY__SHIFT                                                         0x14
#define DAGB0_SDP_WR_PRIORITY__WR_VC0_PRIORITY_MASK                                                           0x0000000FL
#define DAGB0_SDP_WR_PRIORITY__WR_VC1_PRIORITY_MASK                                                           0x000000F0L
#define DAGB0_SDP_WR_PRIORITY__WR_VC2_PRIORITY_MASK                                                           0x00000F00L
#define DAGB0_SDP_WR_PRIORITY__WR_VC3_PRIORITY_MASK                                                           0x0000F000L
#define DAGB0_SDP_WR_PRIORITY__WR_VC4_PRIORITY_MASK                                                           0x000F0000L
#define DAGB0_SDP_WR_PRIORITY__WR_VC5_PRIORITY_MASK                                                           0x00F00000L
//DAGB0_SDP_RD_CLI2SDP_VC_MAP
#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT                                                        0x0
#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT                                                        0x3
#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT                                                      0x6
#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT                                                        0x9
#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT                                                         0xc
#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT                                                        0xf
#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK                                                          0x00000007L
#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK                                                          0x00000038L
#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK                                                        0x000001C0L
#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK                                                          0x00000E00L
#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__IO_VC_MAP_MASK                                                           0x00007000L
#define DAGB0_SDP_RD_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK                                                          0x00038000L
//DAGB0_SDP_WR_CLI2SDP_VC_MAP
#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP__SHIFT                                                        0x0
#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP__SHIFT                                                        0x3
#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP__SHIFT                                                      0x6
#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP__SHIFT                                                        0x9
#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP__SHIFT                                                         0xc
#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP__SHIFT                                                        0xf
#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__SRT_VC_MAP_MASK                                                          0x00000007L
#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__NRT_VC_MAP_MASK                                                          0x00000038L
#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__DLOCK_VC_MAP_MASK                                                        0x000001C0L
#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__HRT_VC_MAP_MASK                                                          0x00000E00L
#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__IO_VC_MAP_MASK                                                           0x00007000L
#define DAGB0_SDP_WR_CLI2SDP_VC_MAP__GMI_VC_MAP_MASK                                                          0x00038000L
//DAGB0_SDP_ENABLE
#define DAGB0_SDP_ENABLE__ENABLE__SHIFT                                                                       0x0
#define DAGB0_SDP_ENABLE__ENABLE_MASK                                                                         0x00000001L
//DAGB0_SDP_CREDITS
#define DAGB0_SDP_CREDITS__TAG_LIMIT__SHIFT                                                                   0x0
#define DAGB0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT                                                             0x8
#define DAGB0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT                                                             0x10
#define DAGB0_SDP_CREDITS__TAG_LIMIT_MASK                                                                     0x000000FFL
#define DAGB0_SDP_CREDITS__WR_RESP_CREDITS_MASK                                                               0x00007F00L
#define DAGB0_SDP_CREDITS__RD_RESP_CREDITS_MASK                                                               0x01FF0000L
//DAGB0_SDP_TAG_RESERVE0
#define DAGB0_SDP_TAG_RESERVE0__VC0__SHIFT                                                                    0x0
#define DAGB0_SDP_TAG_RESERVE0__VC1__SHIFT                                                                    0x8
#define DAGB0_SDP_TAG_RESERVE0__VC2__SHIFT                                                                    0x10
#define DAGB0_SDP_TAG_RESERVE0__VC3__SHIFT                                                                    0x18
#define DAGB0_SDP_TAG_RESERVE0__VC0_MASK                                                                      0x000000FFL
#define DAGB0_SDP_TAG_RESERVE0__VC1_MASK                                                                      0x0000FF00L
#define DAGB0_SDP_TAG_RESERVE0__VC2_MASK                                                                      0x00FF0000L
#define DAGB0_SDP_TAG_RESERVE0__VC3_MASK                                                                      0xFF000000L
//DAGB0_SDP_TAG_RESERVE1
#define DAGB0_SDP_TAG_RESERVE1__VC4__SHIFT                                                                    0x0
#define DAGB0_SDP_TAG_RESERVE1__VC5__SHIFT                                                                    0x8
#define DAGB0_SDP_TAG_RESERVE1__VC6__SHIFT                                                                    0x10
#define DAGB0_SDP_TAG_RESERVE1__VC7__SHIFT                                                                    0x18
#define DAGB0_SDP_TAG_RESERVE1__VC4_MASK                                                                      0x000000FFL
#define DAGB0_SDP_TAG_RESERVE1__VC5_MASK                                                                      0x0000FF00L
#define DAGB0_SDP_TAG_RESERVE1__VC6_MASK                                                                      0x00FF0000L
#define DAGB0_SDP_TAG_RESERVE1__VC7_MASK                                                                      0xFF000000L
//DAGB0_SDP_VCC_RESERVE0
#define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
#define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
#define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
#define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
#define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
#define DAGB0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
#define DAGB0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
#define DAGB0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
#define DAGB0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
#define DAGB0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
//DAGB0_SDP_VCC_RESERVE1
#define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
#define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
#define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
#define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x1f
#define DAGB0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
#define DAGB0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
#define DAGB0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
#define DAGB0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x80000000L
//DAGB0_SDP_ERR_STATUS
#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT                                                         0x0
#define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT                                                         0x4
#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT                                                     0x8
#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT                                               0xa
#define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT                                                       0xb
#define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR__SHIFT                                                            0xc
#define DAGB0_SDP_ERR_STATUS__FUE_FLAG__SHIFT                                                                 0xd
#define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT                                                         0xe
#define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT                                                       0xf
#define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT                                               0x10
#define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT__SHIFT                                                          0x11
#define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT                                                 0x12
#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_STATUS_MASK                                                           0x0000000FL
#define DAGB0_SDP_ERR_STATUS__SDP_WRRSP_STATUS_MASK                                                           0x000000F0L
#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK                                                       0x00000300L
#define DAGB0_SDP_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK                                                 0x00000400L
#define DAGB0_SDP_ERR_STATUS__CLEAR_ERROR_STATUS_MASK                                                         0x00000800L
#define DAGB0_SDP_ERR_STATUS__BUSY_ON_ERROR_MASK                                                              0x00001000L
#define DAGB0_SDP_ERR_STATUS__FUE_FLAG_MASK                                                                   0x00002000L
#define DAGB0_SDP_ERR_STATUS__IGNORE_RDRSP_FED_MASK                                                           0x00004000L
#define DAGB0_SDP_ERR_STATUS__INTERRUPT_ON_FATAL_MASK                                                         0x00008000L
#define DAGB0_SDP_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK                                                 0x00010000L
#define DAGB0_SDP_ERR_STATUS__LEVEL_INTERRUPT_MASK                                                            0x00020000L
#define DAGB0_SDP_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK                                                   0x00040000L
//DAGB0_SDP_REQ_CNTL
#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT                                                  0x0
#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT                                                 0x1
#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT                                                0x2
#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT                                                    0x3
#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT                                                     0x4
#define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT                                                          0x5
#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT                                                       0x6
#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT                                                      0x8
#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT                                                     0xa
#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK                                                    0x00000001L
#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK                                                   0x00000002L
#define DAGB0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK                                                  0x00000004L
#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK                                                      0x00000008L
#define DAGB0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK                                                       0x00000010L
#define DAGB0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK                                                            0x00000020L
#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK                                                         0x000000C0L
#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK                                                        0x00000300L
#define DAGB0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK                                                       0x00000C00L
//DAGB0_SDP_MISC_AON
#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT                                                 0x0
#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT                                              0x2
#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK                                                   0x00000003L
#define DAGB0_SDP_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK                                                0x00000004L
//DAGB0_SDP_MISC
#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0__SHIFT                                                          0x0
#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1__SHIFT                                                          0x1
#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2__SHIFT                                                          0x2
#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3__SHIFT                                                          0x3
#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4__SHIFT                                                          0x4
#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5__SHIFT                                                          0x5
#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6__SHIFT                                                          0x6
#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7__SHIFT                                                          0x7
#define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA__SHIFT                                                             0x8
#define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE__SHIFT                                                           0x9
#define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD__SHIFT                                                         0xb
#define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY__SHIFT                                                        0xd
#define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT                                                         0xf
#define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN__SHIFT                                                           0x14
#define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN__SHIFT                                                           0x15
#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC0_MASK                                                            0x00000001L
#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC1_MASK                                                            0x00000002L
#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC2_MASK                                                            0x00000004L
#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC3_MASK                                                            0x00000008L
#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC4_MASK                                                            0x00000010L
#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC5_MASK                                                            0x00000020L
#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC6_MASK                                                            0x00000040L
#define DAGB0_SDP_MISC__EARLYWRRET_ENABLE_VC7_MASK                                                            0x00000080L
#define DAGB0_SDP_MISC__EARLY_SDP_ORIGDATA_MASK                                                               0x00000100L
#define DAGB0_SDP_MISC__LINKMGR_DYNAMIC_MODE_MASK                                                             0x00000600L
#define DAGB0_SDP_MISC__LINKMGR_HALT_THRESHOLD_MASK                                                           0x00001800L
#define DAGB0_SDP_MISC__LINKMGR_RECONNECT_DELAY_MASK                                                          0x00006000L
#define DAGB0_SDP_MISC__LINKMGR_IDLE_THRESHOLD_MASK                                                           0x000F8000L
#define DAGB0_SDP_MISC__SDP_DAT_FIFO0_MARGIN_MASK                                                             0x00100000L
#define DAGB0_SDP_MISC__SDP_DAT_FIFO1_MARGIN_MASK                                                             0x00200000L
//DAGB0_SDP_MISC2
#define DAGB0_SDP_MISC2__RRET_SWAP_MODE__SHIFT                                                                0x0
#define DAGB0_SDP_MISC2__BLOCK_REQUESTS__SHIFT                                                                0x1
#define DAGB0_SDP_MISC2__REQUESTS_BLOCKED__SHIFT                                                              0x2
#define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE__SHIFT                                                         0x3
#define DAGB0_SDP_MISC2__RRET_SWAP_MODE_MASK                                                                  0x00000001L
#define DAGB0_SDP_MISC2__BLOCK_REQUESTS_MASK                                                                  0x00000002L
#define DAGB0_SDP_MISC2__REQUESTS_BLOCKED_MASK                                                                0x00000004L
#define DAGB0_SDP_MISC2__RDRSP_CR_RELEASE_MODE_MASK                                                           0x00000008L
//DAGB0_SDP_VCD_RESERVE0
#define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT                                                            0x0
#define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT                                                            0x6
#define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT                                                            0xc
#define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT                                                            0x12
#define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT                                                            0x18
#define DAGB0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK                                                              0x0000003FL
#define DAGB0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK                                                              0x00000FC0L
#define DAGB0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK                                                              0x0003F000L
#define DAGB0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK                                                              0x00FC0000L
#define DAGB0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK                                                              0x3F000000L
//DAGB0_SDP_VCD_RESERVE1
#define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT                                                            0x0
#define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT                                                            0x6
#define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT                                                            0xc
#define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT                                                        0x12
#define DAGB0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK                                                              0x0000003FL
#define DAGB0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK                                                              0x00000FC0L
#define DAGB0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK                                                              0x0003F000L
#define DAGB0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK                                                          0x00040000L
//DAGB0_SDP_ARB_CNTL0
#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI__SHIFT                                                        0x0
#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI__SHIFT                                                        0x1
#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES__SHIFT                                                        0x2
#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES__SHIFT                                                        0x3
#define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE__SHIFT                                                        0x4
#define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR__SHIFT                                                         0x5
#define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR__SHIFT                                                          0x6
#define DAGB0_SDP_ARB_CNTL0__DED_MODE__SHIFT                                                                  0x7
#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_PRI_MASK                                                          0x00000001L
#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_PRI_MASK                                                          0x00000002L
#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2RD_ON_RES_MASK                                                          0x00000004L
#define DAGB0_SDP_ARB_CNTL0__EARLY_SW2WR_ON_RES_MASK                                                          0x00000008L
#define DAGB0_SDP_ARB_CNTL0__RW_SWITCH_POP_MODE_MASK                                                          0x00000010L
#define DAGB0_SDP_ARB_CNTL0__ERREVENT_ON_ERROR_MASK                                                           0x00000020L
#define DAGB0_SDP_ARB_CNTL0__HALTREQ_ON_ERROR_MASK                                                            0x00000040L
#define DAGB0_SDP_ARB_CNTL0__DED_MODE_MASK                                                                    0x00000080L
//DAGB0_SDP_ARB_CNTL1
#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL__SHIFT                                                       0x0
#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL__SHIFT                                                       0x8
#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA__SHIFT                                                       0x10
#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA__SHIFT                                                       0x18
#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_CYCL_MASK                                                         0x0000007FL
#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_CYCL_MASK                                                         0x00007F00L
#define DAGB0_SDP_ARB_CNTL1__RD_BURST_LIMIT_DATA_MASK                                                         0x007F0000L
#define DAGB0_SDP_ARB_CNTL1__WR_BURST_LIMIT_DATA_MASK                                                         0x7F000000L
//DAGB0_SDP_CGTT_CLK_CTRL
#define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                              0x0
#define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                        0x5
#define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT                                                  0xd
#define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE__SHIFT                                                            0x1e
#define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT                                                         0x1f
#define DAGB0_SDP_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                0x0000001FL
#define DAGB0_SDP_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                          0x00001FE0L
#define DAGB0_SDP_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK                                                    0x1FFFE000L
#define DAGB0_SDP_CGTT_CLK_CTRL__LS_DISABLE_MASK                                                              0x40000000L
#define DAGB0_SDP_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK                                                           0x80000000L
//DAGB0_SDP_LATENCY_SAMPLING
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT                                                      0x0
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT                                                      0x1
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT                                                       0x2
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT                                                       0x3
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT                                                        0x4
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT                                                        0x5
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT                                                      0x6
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT                                                      0x7
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT                                                     0x8
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT                                                     0x9
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT                                                0xa
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT                                                0xb
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT                                              0xc
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT                                              0xd
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT                                                        0xe
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT                                                        0x16
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK                                                        0x00000001L
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK                                                        0x00000002L
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_GMI_MASK                                                         0x00000004L
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_GMI_MASK                                                         0x00000008L
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_IO_MASK                                                          0x00000010L
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_IO_MASK                                                          0x00000020L
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_READ_MASK                                                        0x00000040L
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_READ_MASK                                                        0x00000080L
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK                                                       0x00000100L
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK                                                       0x00000200L
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK                                                  0x00000400L
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK                                                  0x00000800L
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK                                                0x00001000L
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK                                                0x00002000L
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER0_VC_MASK                                                          0x003FC000L
#define DAGB0_SDP_LATENCY_SAMPLING__SAMPLER1_VC_MASK                                                          0x3FC00000L


// addressBlock: mmhub_pctldec
//PCTL_CTRL
#define PCTL_CTRL__PG_ENABLE__SHIFT                                                                           0x0
#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT                                                               0x1
#define PCTL_CTRL__RSMU_RDTIMER_ENABLE__SHIFT                                                                 0x4
#define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD__SHIFT                                                              0x5
#define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT                                                          0x7
#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT                                                          0xe
#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT                                                      0x13
#define PCTL_CTRL__UTCL2_LEGACY_MODE__SHIFT                                                                   0x14
#define PCTL_CTRL__SDP_DISCONNECT_MODE__SHIFT                                                                 0x15
#define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD__SHIFT                                                           0x16
#define PCTL_CTRL__ZSC_TIMER_ENABLE__SHIFT                                                                    0x1b
#define PCTL_CTRL__Z9_PWRDOWN__SHIFT                                                                          0x1c
#define PCTL_CTRL__Z9_PWRUP__SHIFT                                                                            0x1d
#define PCTL_CTRL__SNR_DISABLE__SHIFT                                                                         0x1e
#define PCTL_CTRL__WRACK_GUARD__SHIFT                                                                         0x1f
#define PCTL_CTRL__PG_ENABLE_MASK                                                                             0x00000001L
#define PCTL_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK                                                                 0x0000000EL
#define PCTL_CTRL__RSMU_RDTIMER_ENABLE_MASK                                                                   0x00000010L
#define PCTL_CTRL__RSMU_RDTIMER_THRESHOLD_MASK                                                                0x00000060L
#define PCTL_CTRL__STCTRL_RSMU_IDLE_THRESHOLD_MASK                                                            0x00003F80L
#define PCTL_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK                                                            0x0007C000L
#define PCTL_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK                                                        0x00080000L
#define PCTL_CTRL__UTCL2_LEGACY_MODE_MASK                                                                     0x00100000L
#define PCTL_CTRL__SDP_DISCONNECT_MODE_MASK                                                                   0x00200000L
#define PCTL_CTRL__STCTRL_ZSC_IDLE_THRESHOLD_MASK                                                             0x07C00000L
#define PCTL_CTRL__ZSC_TIMER_ENABLE_MASK                                                                      0x08000000L
#define PCTL_CTRL__Z9_PWRDOWN_MASK                                                                            0x10000000L
#define PCTL_CTRL__Z9_PWRUP_MASK                                                                              0x20000000L
#define PCTL_CTRL__SNR_DISABLE_MASK                                                                           0x40000000L
#define PCTL_CTRL__WRACK_GUARD_MASK                                                                           0x80000000L
//PCTL_MMHUB_DEEPSLEEP_IB
#define PCTL_MMHUB_DEEPSLEEP_IB__DS0__SHIFT                                                                   0x0
#define PCTL_MMHUB_DEEPSLEEP_IB__DS1__SHIFT                                                                   0x1
#define PCTL_MMHUB_DEEPSLEEP_IB__DS2__SHIFT                                                                   0x2
#define PCTL_MMHUB_DEEPSLEEP_IB__DS3__SHIFT                                                                   0x3
#define PCTL_MMHUB_DEEPSLEEP_IB__DS4__SHIFT                                                                   0x4
#define PCTL_MMHUB_DEEPSLEEP_IB__DS5__SHIFT                                                                   0x5
#define PCTL_MMHUB_DEEPSLEEP_IB__DS6__SHIFT                                                                   0x6
#define PCTL_MMHUB_DEEPSLEEP_IB__DS7__SHIFT                                                                   0x7
#define PCTL_MMHUB_DEEPSLEEP_IB__DS8__SHIFT                                                                   0x8
#define PCTL_MMHUB_DEEPSLEEP_IB__DS9__SHIFT                                                                   0x9
#define PCTL_MMHUB_DEEPSLEEP_IB__DS10__SHIFT                                                                  0xa
#define PCTL_MMHUB_DEEPSLEEP_IB__DS11__SHIFT                                                                  0xb
#define PCTL_MMHUB_DEEPSLEEP_IB__DS12__SHIFT                                                                  0xc
#define PCTL_MMHUB_DEEPSLEEP_IB__DS13__SHIFT                                                                  0xd
#define PCTL_MMHUB_DEEPSLEEP_IB__DS14__SHIFT                                                                  0xe
#define PCTL_MMHUB_DEEPSLEEP_IB__DS15__SHIFT                                                                  0xf
#define PCTL_MMHUB_DEEPSLEEP_IB__DS16__SHIFT                                                                  0x10
#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT                                                              0x1f
#define PCTL_MMHUB_DEEPSLEEP_IB__DS0_MASK                                                                     0x00000001L
#define PCTL_MMHUB_DEEPSLEEP_IB__DS1_MASK                                                                     0x00000002L
#define PCTL_MMHUB_DEEPSLEEP_IB__DS2_MASK                                                                     0x00000004L
#define PCTL_MMHUB_DEEPSLEEP_IB__DS3_MASK                                                                     0x00000008L
#define PCTL_MMHUB_DEEPSLEEP_IB__DS4_MASK                                                                     0x00000010L
#define PCTL_MMHUB_DEEPSLEEP_IB__DS5_MASK                                                                     0x00000020L
#define PCTL_MMHUB_DEEPSLEEP_IB__DS6_MASK                                                                     0x00000040L
#define PCTL_MMHUB_DEEPSLEEP_IB__DS7_MASK                                                                     0x00000080L
#define PCTL_MMHUB_DEEPSLEEP_IB__DS8_MASK                                                                     0x00000100L
#define PCTL_MMHUB_DEEPSLEEP_IB__DS9_MASK                                                                     0x00000200L
#define PCTL_MMHUB_DEEPSLEEP_IB__DS10_MASK                                                                    0x00000400L
#define PCTL_MMHUB_DEEPSLEEP_IB__DS11_MASK                                                                    0x00000800L
#define PCTL_MMHUB_DEEPSLEEP_IB__DS12_MASK                                                                    0x00001000L
#define PCTL_MMHUB_DEEPSLEEP_IB__DS13_MASK                                                                    0x00002000L
#define PCTL_MMHUB_DEEPSLEEP_IB__DS14_MASK                                                                    0x00004000L
#define PCTL_MMHUB_DEEPSLEEP_IB__DS15_MASK                                                                    0x00008000L
#define PCTL_MMHUB_DEEPSLEEP_IB__DS16_MASK                                                                    0x00010000L
#define PCTL_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK                                                                0x80000000L
//PCTL_MMHUB_DEEPSLEEP_OVERRIDE
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT                                                             0x0
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT                                                             0x1
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT                                                             0x2
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT                                                             0x3
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT                                                             0x4
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT                                                             0x5
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT                                                             0x6
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT                                                             0x7
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT                                                             0x8
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT                                                             0x9
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT                                                            0xa
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT                                                            0xb
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT                                                            0xc
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT                                                            0xd
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT                                                            0xe
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT                                                            0xf
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT                                                            0x10
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT                                                        0x11
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK                                                               0x00000001L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK                                                               0x00000002L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK                                                               0x00000004L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK                                                               0x00000008L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK                                                               0x00000010L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK                                                               0x00000020L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK                                                               0x00000040L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK                                                               0x00000080L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK                                                               0x00000100L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK                                                               0x00000200L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK                                                              0x00000400L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK                                                              0x00000800L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK                                                              0x00001000L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK                                                              0x00002000L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK                                                              0x00004000L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK                                                              0x00008000L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK                                                              0x00010000L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK                                                          0x00020000L
//PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT                                                          0x0
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT                                                          0x1
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT                                                          0x2
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT                                                          0x3
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT                                                          0x4
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT                                                          0x5
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT                                                          0x6
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT                                                          0x7
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT                                                          0x8
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT                                                          0x9
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT                                                         0xa
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT                                                         0xb
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT                                                         0xc
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT                                                         0xd
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT                                                         0xe
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT                                                         0xf
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT                                                         0x10
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK                                                            0x00000001L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK                                                            0x00000002L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK                                                            0x00000004L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK                                                            0x00000008L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK                                                            0x00000010L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK                                                            0x00000020L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK                                                            0x00000040L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK                                                            0x00000080L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK                                                            0x00000100L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK                                                            0x00000200L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK                                                           0x00000400L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK                                                           0x00000800L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK                                                           0x00001000L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK                                                           0x00002000L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK                                                           0x00004000L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK                                                           0x00008000L
#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK                                                           0x00010000L
//PCTL_PG_IGNORE_DEEPSLEEP
#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT                                                                  0x0
#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT                                                                  0x1
#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT                                                                  0x2
#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT                                                                  0x3
#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT                                                                  0x4
#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT                                                                  0x5
#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT                                                                  0x6
#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT                                                                  0x7
#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT                                                                  0x8
#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT                                                                  0x9
#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT                                                                 0xa
#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT                                                                 0xb
#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT                                                                 0xc
#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT                                                                 0xd
#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT                                                                 0xe
#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT                                                                 0xf
#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT                                                                 0x10
#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT                                                             0x11
#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT                                                               0x12
#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK                                                                    0x00000001L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK                                                                    0x00000002L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK                                                                    0x00000004L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK                                                                    0x00000008L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK                                                                    0x00000010L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK                                                                    0x00000020L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK                                                                    0x00000040L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK                                                                    0x00000080L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK                                                                    0x00000100L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK                                                                    0x00000200L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK                                                                   0x00000400L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK                                                                   0x00000800L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK                                                                   0x00001000L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK                                                                   0x00002000L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK                                                                   0x00004000L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK                                                                   0x00008000L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK                                                                   0x00010000L
#define PCTL_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK                                                               0x00020000L
#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK                                                                 0x00040000L
//PCTL_PG_IGNORE_DEEPSLEEP_IB
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT                                                               0x0
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT                                                               0x1
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT                                                               0x2
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT                                                               0x3
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT                                                               0x4
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT                                                               0x5
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT                                                               0x6
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT                                                               0x7
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT                                                               0x8
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT                                                               0x9
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT                                                              0xa
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT                                                              0xb
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT                                                              0xc
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT                                                              0xd
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT                                                              0xe
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT                                                              0xf
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT                                                              0x10
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT                                                            0x11
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK                                                                 0x00000001L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK                                                                 0x00000002L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK                                                                 0x00000004L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK                                                                 0x00000008L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK                                                                 0x00000010L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK                                                                 0x00000020L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK                                                                 0x00000040L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK                                                                 0x00000080L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK                                                                 0x00000100L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK                                                                 0x00000200L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK                                                                0x00000400L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK                                                                0x00000800L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK                                                                0x00001000L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK                                                                0x00002000L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK                                                                0x00004000L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK                                                                0x00008000L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK                                                                0x00010000L
#define PCTL_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK                                                              0x00020000L
//PCTL_SLICE0_CFG_DAGB_WRBUSY
#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT                                                          0x0
#define PCTL_SLICE0_CFG_DAGB_WRBUSY__DB_LNCFG_MASK                                                            0xFFFFFFFFL
//PCTL_SLICE0_CFG_DAGB_RDBUSY
#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT                                                          0x0
#define PCTL_SLICE0_CFG_DAGB_RDBUSY__DB_LNCFG_MASK                                                            0xFFFFFFFFL
//PCTL_SLICE0_CFG_DS_ALLOW
#define PCTL_SLICE0_CFG_DS_ALLOW__DS0__SHIFT                                                                  0x0
#define PCTL_SLICE0_CFG_DS_ALLOW__DS1__SHIFT                                                                  0x1
#define PCTL_SLICE0_CFG_DS_ALLOW__DS2__SHIFT                                                                  0x2
#define PCTL_SLICE0_CFG_DS_ALLOW__DS3__SHIFT                                                                  0x3
#define PCTL_SLICE0_CFG_DS_ALLOW__DS4__SHIFT                                                                  0x4
#define PCTL_SLICE0_CFG_DS_ALLOW__DS5__SHIFT                                                                  0x5
#define PCTL_SLICE0_CFG_DS_ALLOW__DS6__SHIFT                                                                  0x6
#define PCTL_SLICE0_CFG_DS_ALLOW__DS7__SHIFT                                                                  0x7
#define PCTL_SLICE0_CFG_DS_ALLOW__DS8__SHIFT                                                                  0x8
#define PCTL_SLICE0_CFG_DS_ALLOW__DS9__SHIFT                                                                  0x9
#define PCTL_SLICE0_CFG_DS_ALLOW__DS10__SHIFT                                                                 0xa
#define PCTL_SLICE0_CFG_DS_ALLOW__DS11__SHIFT                                                                 0xb
#define PCTL_SLICE0_CFG_DS_ALLOW__DS12__SHIFT                                                                 0xc
#define PCTL_SLICE0_CFG_DS_ALLOW__DS13__SHIFT                                                                 0xd
#define PCTL_SLICE0_CFG_DS_ALLOW__DS14__SHIFT                                                                 0xe
#define PCTL_SLICE0_CFG_DS_ALLOW__DS15__SHIFT                                                                 0xf
#define PCTL_SLICE0_CFG_DS_ALLOW__DS16__SHIFT                                                                 0x10
#define PCTL_SLICE0_CFG_DS_ALLOW__DS0_MASK                                                                    0x00000001L
#define PCTL_SLICE0_CFG_DS_ALLOW__DS1_MASK                                                                    0x00000002L
#define PCTL_SLICE0_CFG_DS_ALLOW__DS2_MASK                                                                    0x00000004L
#define PCTL_SLICE0_CFG_DS_ALLOW__DS3_MASK                                                                    0x00000008L
#define PCTL_SLICE0_CFG_DS_ALLOW__DS4_MASK                                                                    0x00000010L
#define PCTL_SLICE0_CFG_DS_ALLOW__DS5_MASK                                                                    0x00000020L
#define PCTL_SLICE0_CFG_DS_ALLOW__DS6_MASK                                                                    0x00000040L
#define PCTL_SLICE0_CFG_DS_ALLOW__DS7_MASK                                                                    0x00000080L
#define PCTL_SLICE0_CFG_DS_ALLOW__DS8_MASK                                                                    0x00000100L
#define PCTL_SLICE0_CFG_DS_ALLOW__DS9_MASK                                                                    0x00000200L
#define PCTL_SLICE0_CFG_DS_ALLOW__DS10_MASK                                                                   0x00000400L
#define PCTL_SLICE0_CFG_DS_ALLOW__DS11_MASK                                                                   0x00000800L
#define PCTL_SLICE0_CFG_DS_ALLOW__DS12_MASK                                                                   0x00001000L
#define PCTL_SLICE0_CFG_DS_ALLOW__DS13_MASK                                                                   0x00002000L
#define PCTL_SLICE0_CFG_DS_ALLOW__DS14_MASK                                                                   0x00004000L
#define PCTL_SLICE0_CFG_DS_ALLOW__DS15_MASK                                                                   0x00008000L
#define PCTL_SLICE0_CFG_DS_ALLOW__DS16_MASK                                                                   0x00010000L
//PCTL_SLICE0_CFG_DS_ALLOW_IB
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT                                                               0x0
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT                                                               0x1
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT                                                               0x2
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT                                                               0x3
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT                                                               0x4
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT                                                               0x5
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT                                                               0x6
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT                                                               0x7
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT                                                               0x8
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT                                                               0x9
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT                                                              0xa
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT                                                              0xb
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT                                                              0xc
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT                                                              0xd
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT                                                              0xe
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT                                                              0xf
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT                                                              0x10
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK                                                                 0x00000001L
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK                                                                 0x00000002L
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK                                                                 0x00000004L
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK                                                                 0x00000008L
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK                                                                 0x00000010L
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK                                                                 0x00000020L
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK                                                                 0x00000040L
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK                                                                 0x00000080L
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK                                                                 0x00000100L
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK                                                                 0x00000200L
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK                                                                0x00000400L
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK                                                                0x00000800L
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK                                                                0x00001000L
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK                                                                0x00002000L
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK                                                                0x00004000L
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK                                                                0x00008000L
#define PCTL_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK                                                                0x00010000L
//PCTL_SLICE1_CFG_DAGB_WRBUSY
#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG__SHIFT                                                          0x0
#define PCTL_SLICE1_CFG_DAGB_WRBUSY__DB_LNCFG_MASK                                                            0xFFFFFFFFL
//PCTL_SLICE1_CFG_DAGB_RDBUSY
#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG__SHIFT                                                          0x0
#define PCTL_SLICE1_CFG_DAGB_RDBUSY__DB_LNCFG_MASK                                                            0xFFFFFFFFL
//PCTL_SLICE1_CFG_DS_ALLOW
#define PCTL_SLICE1_CFG_DS_ALLOW__DS0__SHIFT                                                                  0x0
#define PCTL_SLICE1_CFG_DS_ALLOW__DS1__SHIFT                                                                  0x1
#define PCTL_SLICE1_CFG_DS_ALLOW__DS2__SHIFT                                                                  0x2
#define PCTL_SLICE1_CFG_DS_ALLOW__DS3__SHIFT                                                                  0x3
#define PCTL_SLICE1_CFG_DS_ALLOW__DS4__SHIFT                                                                  0x4
#define PCTL_SLICE1_CFG_DS_ALLOW__DS5__SHIFT                                                                  0x5
#define PCTL_SLICE1_CFG_DS_ALLOW__DS6__SHIFT                                                                  0x6
#define PCTL_SLICE1_CFG_DS_ALLOW__DS7__SHIFT                                                                  0x7
#define PCTL_SLICE1_CFG_DS_ALLOW__DS8__SHIFT                                                                  0x8
#define PCTL_SLICE1_CFG_DS_ALLOW__DS9__SHIFT                                                                  0x9
#define PCTL_SLICE1_CFG_DS_ALLOW__DS10__SHIFT                                                                 0xa
#define PCTL_SLICE1_CFG_DS_ALLOW__DS11__SHIFT                                                                 0xb
#define PCTL_SLICE1_CFG_DS_ALLOW__DS12__SHIFT                                                                 0xc
#define PCTL_SLICE1_CFG_DS_ALLOW__DS13__SHIFT                                                                 0xd
#define PCTL_SLICE1_CFG_DS_ALLOW__DS14__SHIFT                                                                 0xe
#define PCTL_SLICE1_CFG_DS_ALLOW__DS15__SHIFT                                                                 0xf
#define PCTL_SLICE1_CFG_DS_ALLOW__DS16__SHIFT                                                                 0x10
#define PCTL_SLICE1_CFG_DS_ALLOW__DS0_MASK                                                                    0x00000001L
#define PCTL_SLICE1_CFG_DS_ALLOW__DS1_MASK                                                                    0x00000002L
#define PCTL_SLICE1_CFG_DS_ALLOW__DS2_MASK                                                                    0x00000004L
#define PCTL_SLICE1_CFG_DS_ALLOW__DS3_MASK                                                                    0x00000008L
#define PCTL_SLICE1_CFG_DS_ALLOW__DS4_MASK                                                                    0x00000010L
#define PCTL_SLICE1_CFG_DS_ALLOW__DS5_MASK                                                                    0x00000020L
#define PCTL_SLICE1_CFG_DS_ALLOW__DS6_MASK                                                                    0x00000040L
#define PCTL_SLICE1_CFG_DS_ALLOW__DS7_MASK                                                                    0x00000080L
#define PCTL_SLICE1_CFG_DS_ALLOW__DS8_MASK                                                                    0x00000100L
#define PCTL_SLICE1_CFG_DS_ALLOW__DS9_MASK                                                                    0x00000200L
#define PCTL_SLICE1_CFG_DS_ALLOW__DS10_MASK                                                                   0x00000400L
#define PCTL_SLICE1_CFG_DS_ALLOW__DS11_MASK                                                                   0x00000800L
#define PCTL_SLICE1_CFG_DS_ALLOW__DS12_MASK                                                                   0x00001000L
#define PCTL_SLICE1_CFG_DS_ALLOW__DS13_MASK                                                                   0x00002000L
#define PCTL_SLICE1_CFG_DS_ALLOW__DS14_MASK                                                                   0x00004000L
#define PCTL_SLICE1_CFG_DS_ALLOW__DS15_MASK                                                                   0x00008000L
#define PCTL_SLICE1_CFG_DS_ALLOW__DS16_MASK                                                                   0x00010000L
//PCTL_SLICE1_CFG_DS_ALLOW_IB
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT                                                               0x0
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT                                                               0x1
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT                                                               0x2
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT                                                               0x3
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT                                                               0x4
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT                                                               0x5
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT                                                               0x6
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT                                                               0x7
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT                                                               0x8
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT                                                               0x9
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT                                                              0xa
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT                                                              0xb
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT                                                              0xc
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT                                                              0xd
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT                                                              0xe
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT                                                              0xf
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT                                                              0x10
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK                                                                 0x00000001L
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK                                                                 0x00000002L
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK                                                                 0x00000004L
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK                                                                 0x00000008L
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK                                                                 0x00000010L
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK                                                                 0x00000020L
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK                                                                 0x00000040L
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK                                                                 0x00000080L
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK                                                                 0x00000100L
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK                                                                 0x00000200L
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK                                                                0x00000400L
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK                                                                0x00000800L
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK                                                                0x00001000L
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK                                                                0x00002000L
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK                                                                0x00004000L
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK                                                                0x00008000L
#define PCTL_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK                                                                0x00010000L
//PCTL_UTCL2_MISC
#define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT                                              0x0
#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT                                                            0xb
#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                           0xc
#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                            0xf
#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                   0x10
#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                    0x11
#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT                                                               0x12
#define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE__SHIFT                                                            0x13
#define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER__SHIFT                                                             0x14
#define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER__SHIFT                                                          0x1a
#define PCTL_UTCL2_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK                                                0x000007FFL
#define PCTL_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK                                                              0x00000800L
#define PCTL_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK                                                             0x00007000L
#define PCTL_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK                                                              0x00008000L
#define PCTL_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                     0x00010000L
#define PCTL_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                      0x00020000L
#define PCTL_UTCL2_MISC__RD_TIMER_ENABLE_MASK                                                                 0x00040000L
#define PCTL_UTCL2_MISC__RENG_MEM_DS_ENABLE_MASK                                                              0x00080000L
#define PCTL_UTCL2_MISC__RENG_MEM_LS_TIMER_MASK                                                               0x03F00000L
#define PCTL_UTCL2_MISC__RENG_MEM_SLEEP_TIMER_MASK                                                            0x3C000000L
//PCTL_SLICE0_MISC
#define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT                                             0x0
#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT                                                           0xa
#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                          0xb
#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                           0xe
#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                  0xf
#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                            0x10
#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                   0x11
#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT                                                              0x12
#define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE__SHIFT                                                           0x13
#define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER__SHIFT                                                            0x14
#define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER__SHIFT                                                         0x1a
#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK__SHIFT                                                          0x1e
#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK__SHIFT                                                          0x1f
#define PCTL_SLICE0_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK                                               0x000003FFL
#define PCTL_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK                                                             0x00000400L
#define PCTL_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK                                                            0x00003800L
#define PCTL_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK                                                             0x00004000L
#define PCTL_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                    0x00008000L
#define PCTL_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK                                                              0x00010000L
#define PCTL_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                     0x00020000L
#define PCTL_SLICE0_MISC__RD_TIMER_ENABLE_MASK                                                                0x00040000L
#define PCTL_SLICE0_MISC__RENG_MEM_DS_ENABLE_MASK                                                             0x00080000L
#define PCTL_SLICE0_MISC__RENG_MEM_LS_TIMER_MASK                                                              0x03F00000L
#define PCTL_SLICE0_MISC__RENG_MEM_SLEEP_TIMER_MASK                                                           0x3C000000L
#define PCTL_SLICE0_MISC__OVR_EA_SDP0_PARTACK_MASK                                                            0x40000000L
#define PCTL_SLICE0_MISC__OVR_EA_SDP0_FULLACK_MASK                                                            0x80000000L
//PCTL_SLICE1_MISC
#define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR__SHIFT                                             0x0
#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT                                                           0xa
#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT                                                          0xb
#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT                                                           0xe
#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT                                                  0xf
#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT                                                            0x10
#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT                                                   0x11
#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT                                                              0x12
#define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE__SHIFT                                                           0x13
#define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER__SHIFT                                                            0x14
#define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER__SHIFT                                                         0x1a
#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK__SHIFT                                                          0x1e
#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK__SHIFT                                                          0x1f
#define PCTL_SLICE1_MISC__RENG_EXECUTE_NONSECURE_START_PTR_MASK                                               0x000003FFL
#define PCTL_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK                                                             0x00000400L
#define PCTL_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK                                                            0x00003800L
#define PCTL_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK                                                             0x00004000L
#define PCTL_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK                                                    0x00008000L
#define PCTL_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK                                                              0x00010000L
#define PCTL_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK                                                     0x00020000L
#define PCTL_SLICE1_MISC__RD_TIMER_ENABLE_MASK                                                                0x00040000L
#define PCTL_SLICE1_MISC__RENG_MEM_DS_ENABLE_MASK                                                             0x00080000L
#define PCTL_SLICE1_MISC__RENG_MEM_LS_TIMER_MASK                                                              0x03F00000L
#define PCTL_SLICE1_MISC__RENG_MEM_SLEEP_TIMER_MASK                                                           0x3C000000L
#define PCTL_SLICE1_MISC__OVR_EA_SDP1_PARTACK_MASK                                                            0x40000000L
#define PCTL_SLICE1_MISC__OVR_EA_SDP1_FULLACK_MASK                                                            0x80000000L
//PCTL_RENG_CTRL
#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW__SHIFT                                                               0x0
#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE__SHIFT                                                          0x1
#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MASK                                                                 0x00000001L
#define PCTL_RENG_CTRL__RENG_EXECUTE_NOW_MODE_MASK                                                            0x00000002L
//PCTL_UTCL2_RENG_EXECUTE
#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                      0x0
#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                                 0x1
#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                            0x2
#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                  0xd
#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                        0x00000001L
#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                   0x00000002L
#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                              0x00001FFCL
#define PCTL_UTCL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                    0x00FFE000L
//PCTL_SLICE0_RENG_EXECUTE
#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                     0x0
#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                                0x1
#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                           0x2
#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                 0xc
#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                       0x00000001L
#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                  0x00000002L
#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                             0x00000FFCL
#define PCTL_SLICE0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                   0x003FF000L
//PCTL_SLICE1_RENG_EXECUTE
#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT                                                     0x0
#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT                                                0x1
#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT                                           0x2
#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT                                                 0xc
#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK                                                       0x00000001L
#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK                                                  0x00000002L
#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK                                             0x00000FFCL
#define PCTL_SLICE1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK                                                   0x003FF000L
//PCTL_UTCL2_RENG_RAM_INDEX
#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                      0x0
#define PCTL_UTCL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                        0x000007FFL
//PCTL_UTCL2_RENG_RAM_DATA
#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                        0x0
#define PCTL_UTCL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                          0xFFFFFFFFL
//PCTL_SLICE0_RENG_RAM_INDEX
#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                     0x0
#define PCTL_SLICE0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                       0x000003FFL
//PCTL_SLICE0_RENG_RAM_DATA
#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                       0x0
#define PCTL_SLICE0_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                         0xFFFFFFFFL
//PCTL_SLICE1_RENG_RAM_INDEX
#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT                                                     0x0
#define PCTL_SLICE1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK                                                       0x000003FFL
//PCTL_SLICE1_RENG_RAM_DATA
#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT                                                       0x0
#define PCTL_SLICE1_RENG_RAM_DATA__RENG_RAM_DATA_MASK                                                         0xFFFFFFFFL
//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                              0x0
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                             0x10
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                                0x0000FFFFL
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                               0xFFFF0000L
//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                              0x0
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                             0x10
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                                0x0000FFFFL
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                               0xFFFF0000L
//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                              0x0
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                             0x10
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                                0x0000FFFFL
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                               0xFFFF0000L
//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                              0x0
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                             0x10
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                                0x0000FFFFL
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                               0xFFFF0000L
//PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                              0x0
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                             0x10
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                                0x0000FFFFL
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                               0xFFFF0000L
//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                          0x0
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                          0x10
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                            0x0000FFFFL
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                            0xFFFF0000L
//PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT                          0x0
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT                          0x10
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK                            0x0000FFFFL
#define PCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK                            0xFFFF0000L
//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
//PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                         0x0
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                         0x10
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                           0x0000FFFFL
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                           0xFFFF0000L
//PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT                         0x0
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT                         0x10
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK                           0x0000FFFFL
#define PCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK                           0xFFFF0000L
//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
//PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE__SHIFT                             0x0
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT__SHIFT                            0x10
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_BASE_MASK                               0x0000FFFFL
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4__STCTRL_REGISTER_SAVE_LIMIT_MASK                              0xFFFF0000L
//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0__SHIFT                         0x0
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1__SHIFT                         0x10
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL0_MASK                           0x0000FFFFL
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0__STCTRL_REGISTER_SAVE_EXCL1_MASK                           0xFFFF0000L
//PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT                         0x0
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT                         0x10
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK                           0x0000FFFFL
#define PCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK                           0xFFFF0000L
//PCTL_STATUS
#define PCTL_STATUS__MMHUB_CONFIG_DONE__SHIFT                                                                 0x0
#define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE__SHIFT                                                            0x1
#define PCTL_STATUS__MMHUB_FENCE_REQ__SHIFT                                                                   0x2
#define PCTL_STATUS__MMHUB_FENCE_ACK__SHIFT                                                                   0x3
#define PCTL_STATUS__MMHUB_IDLE__SHIFT                                                                        0x4
#define PCTL_STATUS__PGFSM_CMD_STATUS__SHIFT                                                                  0x5
#define PCTL_STATUS__RSMU_RDTIMEOUT_CNT__SHIFT                                                                0x7
#define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR__SHIFT                                                              0xf
#define PCTL_STATUS__MMHUB_POWER__SHIFT                                                                       0x10
#define PCTL_STATUS__RENG_RAM_STALE__SHIFT                                                                    0x11
#define PCTL_STATUS__UTCL2_RENG_RAM_STALE__SHIFT                                                              0x12
#define PCTL_STATUS__SLICE0_RENG_RAM_STALE__SHIFT                                                             0x13
#define PCTL_STATUS__SLICE1_RENG_RAM_STALE__SHIFT                                                             0x14
#define PCTL_STATUS__MMHUB_CONFIG_DONE_MASK                                                                   0x00000001L
#define PCTL_STATUS__MMHUB_INTERLOCK_ENABLE_MASK                                                              0x00000002L
#define PCTL_STATUS__MMHUB_FENCE_REQ_MASK                                                                     0x00000004L
#define PCTL_STATUS__MMHUB_FENCE_ACK_MASK                                                                     0x00000008L
#define PCTL_STATUS__MMHUB_IDLE_MASK                                                                          0x00000010L
#define PCTL_STATUS__PGFSM_CMD_STATUS_MASK                                                                    0x00000060L
#define PCTL_STATUS__RSMU_RDTIMEOUT_CNT_MASK                                                                  0x00007F80L
#define PCTL_STATUS__RSMU_RDTIMEOUT_CLEAR_MASK                                                                0x00008000L
#define PCTL_STATUS__MMHUB_POWER_MASK                                                                         0x00010000L
#define PCTL_STATUS__RENG_RAM_STALE_MASK                                                                      0x00020000L
#define PCTL_STATUS__UTCL2_RENG_RAM_STALE_MASK                                                                0x00040000L
#define PCTL_STATUS__SLICE0_RENG_RAM_STALE_MASK                                                               0x00080000L
#define PCTL_STATUS__SLICE1_RENG_RAM_STALE_MASK                                                               0x00100000L
//PCTL_PERFCOUNTER_LO
#define PCTL_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                                0x0
#define PCTL_PERFCOUNTER_LO__COUNTER_LO_MASK                                                                  0xFFFFFFFFL
//PCTL_PERFCOUNTER_HI
#define PCTL_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                                0x0
#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                             0x10
#define PCTL_PERFCOUNTER_HI__COUNTER_HI_MASK                                                                  0x0000FFFFL
#define PCTL_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                               0xFFFF0000L
//PCTL_PERFCOUNTER0_CFG
#define PCTL_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                                0x0
#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                            0x8
#define PCTL_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                               0x18
#define PCTL_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                                  0x1c
#define PCTL_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                   0x1d
#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                                  0x000000FFL
#define PCTL_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                              0x0000FF00L
#define PCTL_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                                 0x0F000000L
#define PCTL_PERFCOUNTER0_CFG__ENABLE_MASK                                                                    0x10000000L
#define PCTL_PERFCOUNTER0_CFG__CLEAR_MASK                                                                     0x20000000L
//PCTL_PERFCOUNTER1_CFG
#define PCTL_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                                0x0
#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                            0x8
#define PCTL_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                               0x18
#define PCTL_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                                  0x1c
#define PCTL_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                   0x1d
#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                                  0x000000FFL
#define PCTL_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                              0x0000FF00L
#define PCTL_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                                 0x0F000000L
#define PCTL_PERFCOUNTER1_CFG__ENABLE_MASK                                                                    0x10000000L
#define PCTL_PERFCOUNTER1_CFG__CLEAR_MASK                                                                     0x20000000L
//PCTL_PERFCOUNTER_RSLT_CNTL
#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                                0x0
#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                      0x8
#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                       0x10
#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                         0x18
#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                          0x19
#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                               0x1a
#define PCTL_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                                  0x0000000FL
#define PCTL_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                        0x0000FF00L
#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                         0x00FF0000L
#define PCTL_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                           0x01000000L
#define PCTL_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                            0x02000000L
#define PCTL_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                                 0x04000000L
//PCTL_RESERVED_0
#define PCTL_RESERVED_0__WORD__SHIFT                                                                          0x0
#define PCTL_RESERVED_0__BYTE__SHIFT                                                                          0x10
#define PCTL_RESERVED_0__BIT7__SHIFT                                                                          0x18
#define PCTL_RESERVED_0__BIT6__SHIFT                                                                          0x19
#define PCTL_RESERVED_0__BIT5__SHIFT                                                                          0x1a
#define PCTL_RESERVED_0__BIT4__SHIFT                                                                          0x1b
#define PCTL_RESERVED_0__BIT3__SHIFT                                                                          0x1c
#define PCTL_RESERVED_0__BIT2__SHIFT                                                                          0x1d
#define PCTL_RESERVED_0__BIT1__SHIFT                                                                          0x1e
#define PCTL_RESERVED_0__BIT0__SHIFT                                                                          0x1f
#define PCTL_RESERVED_0__WORD_MASK                                                                            0x0000FFFFL
#define PCTL_RESERVED_0__BYTE_MASK                                                                            0x00FF0000L
#define PCTL_RESERVED_0__BIT7_MASK                                                                            0x01000000L
#define PCTL_RESERVED_0__BIT6_MASK                                                                            0x02000000L
#define PCTL_RESERVED_0__BIT5_MASK                                                                            0x04000000L
#define PCTL_RESERVED_0__BIT4_MASK                                                                            0x08000000L
#define PCTL_RESERVED_0__BIT3_MASK                                                                            0x10000000L
#define PCTL_RESERVED_0__BIT2_MASK                                                                            0x20000000L
#define PCTL_RESERVED_0__BIT1_MASK                                                                            0x40000000L
#define PCTL_RESERVED_0__BIT0_MASK                                                                            0x80000000L
//PCTL_RESERVED_1
#define PCTL_RESERVED_1__WORD__SHIFT                                                                          0x0
#define PCTL_RESERVED_1__BYTE__SHIFT                                                                          0x10
#define PCTL_RESERVED_1__BIT7__SHIFT                                                                          0x18
#define PCTL_RESERVED_1__BIT6__SHIFT                                                                          0x19
#define PCTL_RESERVED_1__BIT5__SHIFT                                                                          0x1a
#define PCTL_RESERVED_1__BIT4__SHIFT                                                                          0x1b
#define PCTL_RESERVED_1__BIT3__SHIFT                                                                          0x1c
#define PCTL_RESERVED_1__BIT2__SHIFT                                                                          0x1d
#define PCTL_RESERVED_1__BIT1__SHIFT                                                                          0x1e
#define PCTL_RESERVED_1__BIT0__SHIFT                                                                          0x1f
#define PCTL_RESERVED_1__WORD_MASK                                                                            0x0000FFFFL
#define PCTL_RESERVED_1__BYTE_MASK                                                                            0x00FF0000L
#define PCTL_RESERVED_1__BIT7_MASK                                                                            0x01000000L
#define PCTL_RESERVED_1__BIT6_MASK                                                                            0x02000000L
#define PCTL_RESERVED_1__BIT5_MASK                                                                            0x04000000L
#define PCTL_RESERVED_1__BIT4_MASK                                                                            0x08000000L
#define PCTL_RESERVED_1__BIT3_MASK                                                                            0x10000000L
#define PCTL_RESERVED_1__BIT2_MASK                                                                            0x20000000L
#define PCTL_RESERVED_1__BIT1_MASK                                                                            0x40000000L
#define PCTL_RESERVED_1__BIT0_MASK                                                                            0x80000000L
//PCTL_RESERVED_2
#define PCTL_RESERVED_2__WORD__SHIFT                                                                          0x0
#define PCTL_RESERVED_2__BYTE__SHIFT                                                                          0x10
#define PCTL_RESERVED_2__BIT7__SHIFT                                                                          0x18
#define PCTL_RESERVED_2__BIT6__SHIFT                                                                          0x19
#define PCTL_RESERVED_2__BIT5__SHIFT                                                                          0x1a
#define PCTL_RESERVED_2__BIT4__SHIFT                                                                          0x1b
#define PCTL_RESERVED_2__BIT3__SHIFT                                                                          0x1c
#define PCTL_RESERVED_2__BIT2__SHIFT                                                                          0x1d
#define PCTL_RESERVED_2__BIT1__SHIFT                                                                          0x1e
#define PCTL_RESERVED_2__BIT0__SHIFT                                                                          0x1f
#define PCTL_RESERVED_2__WORD_MASK                                                                            0x0000FFFFL
#define PCTL_RESERVED_2__BYTE_MASK                                                                            0x00FF0000L
#define PCTL_RESERVED_2__BIT7_MASK                                                                            0x01000000L
#define PCTL_RESERVED_2__BIT6_MASK                                                                            0x02000000L
#define PCTL_RESERVED_2__BIT5_MASK                                                                            0x04000000L
#define PCTL_RESERVED_2__BIT4_MASK                                                                            0x08000000L
#define PCTL_RESERVED_2__BIT3_MASK                                                                            0x10000000L
#define PCTL_RESERVED_2__BIT2_MASK                                                                            0x20000000L
#define PCTL_RESERVED_2__BIT1_MASK                                                                            0x40000000L
#define PCTL_RESERVED_2__BIT0_MASK                                                                            0x80000000L
//PCTL_RESERVED_3
#define PCTL_RESERVED_3__WORD__SHIFT                                                                          0x0
#define PCTL_RESERVED_3__BYTE__SHIFT                                                                          0x10
#define PCTL_RESERVED_3__BIT7__SHIFT                                                                          0x18
#define PCTL_RESERVED_3__BIT6__SHIFT                                                                          0x19
#define PCTL_RESERVED_3__BIT5__SHIFT                                                                          0x1a
#define PCTL_RESERVED_3__BIT4__SHIFT                                                                          0x1b
#define PCTL_RESERVED_3__BIT3__SHIFT                                                                          0x1c
#define PCTL_RESERVED_3__BIT2__SHIFT                                                                          0x1d
#define PCTL_RESERVED_3__BIT1__SHIFT                                                                          0x1e
#define PCTL_RESERVED_3__BIT0__SHIFT                                                                          0x1f
#define PCTL_RESERVED_3__WORD_MASK                                                                            0x0000FFFFL
#define PCTL_RESERVED_3__BYTE_MASK                                                                            0x00FF0000L
#define PCTL_RESERVED_3__BIT7_MASK                                                                            0x01000000L
#define PCTL_RESERVED_3__BIT6_MASK                                                                            0x02000000L
#define PCTL_RESERVED_3__BIT5_MASK                                                                            0x04000000L
#define PCTL_RESERVED_3__BIT4_MASK                                                                            0x08000000L
#define PCTL_RESERVED_3__BIT3_MASK                                                                            0x10000000L
#define PCTL_RESERVED_3__BIT2_MASK                                                                            0x20000000L
#define PCTL_RESERVED_3__BIT1_MASK                                                                            0x40000000L
#define PCTL_RESERVED_3__BIT0_MASK                                                                            0x80000000L


// addressBlock: mmhub_l1tlb_mmutcl1pfdec
//MMMC_VM_MX_L1_TLB0_STATUS
#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT                                                                0x0
#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                               0x2
#define MMMC_VM_MX_L1_TLB0_STATUS__BUSY_MASK                                                                  0x00000001L
#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
#define MMMC_VM_MX_L1_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK                                                 0x00000004L
//MMMC_VM_MX_L1_TLB1_STATUS
#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT                                                                0x0
#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                               0x2
#define MMMC_VM_MX_L1_TLB1_STATUS__BUSY_MASK                                                                  0x00000001L
#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
#define MMMC_VM_MX_L1_TLB1_STATUS__FOUND_APERTURE_FAULTS_MASK                                                 0x00000004L
//MMMC_VM_MX_L1_TLB2_STATUS
#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT                                                                0x0
#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                               0x2
#define MMMC_VM_MX_L1_TLB2_STATUS__BUSY_MASK                                                                  0x00000001L
#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
#define MMMC_VM_MX_L1_TLB2_STATUS__FOUND_APERTURE_FAULTS_MASK                                                 0x00000004L
//MMMC_VM_MX_L1_TLB3_STATUS
#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT                                                                0x0
#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                               0x2
#define MMMC_VM_MX_L1_TLB3_STATUS__BUSY_MASK                                                                  0x00000001L
#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
#define MMMC_VM_MX_L1_TLB3_STATUS__FOUND_APERTURE_FAULTS_MASK                                                 0x00000004L
//MMMC_VM_MX_L1_TLB4_STATUS
#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT                                                                0x0
#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                               0x2
#define MMMC_VM_MX_L1_TLB4_STATUS__BUSY_MASK                                                                  0x00000001L
#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
#define MMMC_VM_MX_L1_TLB4_STATUS__FOUND_APERTURE_FAULTS_MASK                                                 0x00000004L
//MMMC_VM_MX_L1_TLB5_STATUS
#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT                                                                0x0
#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                               0x2
#define MMMC_VM_MX_L1_TLB5_STATUS__BUSY_MASK                                                                  0x00000001L
#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
#define MMMC_VM_MX_L1_TLB5_STATUS__FOUND_APERTURE_FAULTS_MASK                                                 0x00000004L
//MMMC_VM_MX_L1_TLB6_STATUS
#define MMMC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT                                                                0x0
#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                               0x2
#define MMMC_VM_MX_L1_TLB6_STATUS__BUSY_MASK                                                                  0x00000001L
#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
#define MMMC_VM_MX_L1_TLB6_STATUS__FOUND_APERTURE_FAULTS_MASK                                                 0x00000004L
//MMMC_VM_MX_L1_TLB7_STATUS
#define MMMC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT                                                                0x0
#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                 0x1
#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                               0x2
#define MMMC_VM_MX_L1_TLB7_STATUS__BUSY_MASK                                                                  0x00000001L
#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK                                                   0x00000002L
#define MMMC_VM_MX_L1_TLB7_STATUS__FOUND_APERTURE_FAULTS_MASK                                                 0x00000004L


// addressBlock: mmhub_l1tlb_mmutcl1pldec
//MMMC_VM_MX_L1_PERFCOUNTER0_CFG
#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                   0x8
#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                      0x18
#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                         0x1c
#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                          0x1d
#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                         0x000000FFL
#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                        0x0F000000L
#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK                                                           0x10000000L
#define MMMC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK                                                            0x20000000L
//MMMC_VM_MX_L1_PERFCOUNTER1_CFG
#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                   0x8
#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                      0x18
#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                         0x1c
#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                          0x1d
#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                         0x000000FFL
#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                        0x0F000000L
#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK                                                           0x10000000L
#define MMMC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK                                                            0x20000000L
//MMMC_VM_MX_L1_PERFCOUNTER2_CFG
#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                   0x8
#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                      0x18
#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                         0x1c
#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                          0x1d
#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                         0x000000FFL
#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                        0x0F000000L
#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK                                                           0x10000000L
#define MMMC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK                                                            0x20000000L
//MMMC_VM_MX_L1_PERFCOUNTER3_CFG
#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                   0x8
#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                      0x18
#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                         0x1c
#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                          0x1d
#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                         0x000000FFL
#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                        0x0F000000L
#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK                                                           0x10000000L
#define MMMC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK                                                            0x20000000L
//MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL
#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                       0x0
#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                             0x8
#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                              0x10
#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                0x18
#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                 0x19
#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                      0x1a
#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                         0x0000000FL
#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                               0x0000FF00L
#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                0x00FF0000L
#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                  0x01000000L
#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                   0x02000000L
#define MMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                        0x04000000L


// addressBlock: mmhub_l1tlb_mmutcl1prdec
//MMMC_VM_MX_L1_PERFCOUNTER_LO
#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK                                                         0xFFFFFFFFL
//MMMC_VM_MX_L1_PERFCOUNTER_HI
#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                    0x10
#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK                                                         0x0000FFFFL
#define MMMC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                      0xFFFF0000L


// addressBlock: mmhub_l1tlb_mmvmtlspfdec
//MMMC_VM_MX_L1_TLS0_CNTL
#define MMMC_VM_MX_L1_TLS0_CNTL__PREFETCH_COUNT__SHIFT                                                        0x0
#define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                    0x4
#define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT                 0x5
#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_SNOOP_SELECT__SHIFT                                                    0x6
#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SYSTEM__SHIFT                                                  0x8
#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SNOOP__SHIFT                                                   0x9
#define MMMC_VM_MX_L1_TLS0_CNTL__DEBUG_ECO_BITS__SHIFT                                                        0x10
#define MMMC_VM_MX_L1_TLS0_CNTL__PREFETCH_COUNT_MASK                                                          0x0000000FL
#define MMMC_VM_MX_L1_TLS0_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                      0x00000010L
#define MMMC_VM_MX_L1_TLS0_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK                   0x00000020L
#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_SNOOP_SELECT_MASK                                                      0x000000C0L
#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SYSTEM_MASK                                                    0x00000100L
#define MMMC_VM_MX_L1_TLS0_CNTL__IOMGR_DEFAULT_SNOOP_MASK                                                     0x00000200L
#define MMMC_VM_MX_L1_TLS0_CNTL__DEBUG_ECO_BITS_MASK                                                          0xFFFF0000L
//MMMC_VM_MX_L1_TLS0_CNTL0
#define MMMC_VM_MX_L1_TLS0_CNTL0__REQ_STREAM_ID__SHIFT                                                        0x0
#define MMMC_VM_MX_L1_TLS0_CNTL0__EN__SHIFT                                                                   0xc
#define MMMC_VM_MX_L1_TLS0_CNTL0__PREFETCH_DONE__SHIFT                                                        0xd
#define MMMC_VM_MX_L1_TLS0_CNTL0__REQ_STREAM_ID_MASK                                                          0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL0__EN_MASK                                                                     0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL0__PREFETCH_DONE_MASK                                                          0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL1
#define MMMC_VM_MX_L1_TLS0_CNTL1__REQ_STREAM_ID__SHIFT                                                        0x0
#define MMMC_VM_MX_L1_TLS0_CNTL1__EN__SHIFT                                                                   0xc
#define MMMC_VM_MX_L1_TLS0_CNTL1__PREFETCH_DONE__SHIFT                                                        0xd
#define MMMC_VM_MX_L1_TLS0_CNTL1__REQ_STREAM_ID_MASK                                                          0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL1__EN_MASK                                                                     0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL1__PREFETCH_DONE_MASK                                                          0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL2
#define MMMC_VM_MX_L1_TLS0_CNTL2__REQ_STREAM_ID__SHIFT                                                        0x0
#define MMMC_VM_MX_L1_TLS0_CNTL2__EN__SHIFT                                                                   0xc
#define MMMC_VM_MX_L1_TLS0_CNTL2__PREFETCH_DONE__SHIFT                                                        0xd
#define MMMC_VM_MX_L1_TLS0_CNTL2__REQ_STREAM_ID_MASK                                                          0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL2__EN_MASK                                                                     0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL2__PREFETCH_DONE_MASK                                                          0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL3
#define MMMC_VM_MX_L1_TLS0_CNTL3__REQ_STREAM_ID__SHIFT                                                        0x0
#define MMMC_VM_MX_L1_TLS0_CNTL3__EN__SHIFT                                                                   0xc
#define MMMC_VM_MX_L1_TLS0_CNTL3__PREFETCH_DONE__SHIFT                                                        0xd
#define MMMC_VM_MX_L1_TLS0_CNTL3__REQ_STREAM_ID_MASK                                                          0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL3__EN_MASK                                                                     0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL3__PREFETCH_DONE_MASK                                                          0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL4
#define MMMC_VM_MX_L1_TLS0_CNTL4__REQ_STREAM_ID__SHIFT                                                        0x0
#define MMMC_VM_MX_L1_TLS0_CNTL4__EN__SHIFT                                                                   0xc
#define MMMC_VM_MX_L1_TLS0_CNTL4__PREFETCH_DONE__SHIFT                                                        0xd
#define MMMC_VM_MX_L1_TLS0_CNTL4__REQ_STREAM_ID_MASK                                                          0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL4__EN_MASK                                                                     0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL4__PREFETCH_DONE_MASK                                                          0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL5
#define MMMC_VM_MX_L1_TLS0_CNTL5__REQ_STREAM_ID__SHIFT                                                        0x0
#define MMMC_VM_MX_L1_TLS0_CNTL5__EN__SHIFT                                                                   0xc
#define MMMC_VM_MX_L1_TLS0_CNTL5__PREFETCH_DONE__SHIFT                                                        0xd
#define MMMC_VM_MX_L1_TLS0_CNTL5__REQ_STREAM_ID_MASK                                                          0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL5__EN_MASK                                                                     0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL5__PREFETCH_DONE_MASK                                                          0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL6
#define MMMC_VM_MX_L1_TLS0_CNTL6__REQ_STREAM_ID__SHIFT                                                        0x0
#define MMMC_VM_MX_L1_TLS0_CNTL6__EN__SHIFT                                                                   0xc
#define MMMC_VM_MX_L1_TLS0_CNTL6__PREFETCH_DONE__SHIFT                                                        0xd
#define MMMC_VM_MX_L1_TLS0_CNTL6__REQ_STREAM_ID_MASK                                                          0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL6__EN_MASK                                                                     0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL6__PREFETCH_DONE_MASK                                                          0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL7
#define MMMC_VM_MX_L1_TLS0_CNTL7__REQ_STREAM_ID__SHIFT                                                        0x0
#define MMMC_VM_MX_L1_TLS0_CNTL7__EN__SHIFT                                                                   0xc
#define MMMC_VM_MX_L1_TLS0_CNTL7__PREFETCH_DONE__SHIFT                                                        0xd
#define MMMC_VM_MX_L1_TLS0_CNTL7__REQ_STREAM_ID_MASK                                                          0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL7__EN_MASK                                                                     0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL7__PREFETCH_DONE_MASK                                                          0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL8
#define MMMC_VM_MX_L1_TLS0_CNTL8__REQ_STREAM_ID__SHIFT                                                        0x0
#define MMMC_VM_MX_L1_TLS0_CNTL8__EN__SHIFT                                                                   0xc
#define MMMC_VM_MX_L1_TLS0_CNTL8__PREFETCH_DONE__SHIFT                                                        0xd
#define MMMC_VM_MX_L1_TLS0_CNTL8__REQ_STREAM_ID_MASK                                                          0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL8__EN_MASK                                                                     0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL8__PREFETCH_DONE_MASK                                                          0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL9
#define MMMC_VM_MX_L1_TLS0_CNTL9__REQ_STREAM_ID__SHIFT                                                        0x0
#define MMMC_VM_MX_L1_TLS0_CNTL9__EN__SHIFT                                                                   0xc
#define MMMC_VM_MX_L1_TLS0_CNTL9__PREFETCH_DONE__SHIFT                                                        0xd
#define MMMC_VM_MX_L1_TLS0_CNTL9__REQ_STREAM_ID_MASK                                                          0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL9__EN_MASK                                                                     0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL9__PREFETCH_DONE_MASK                                                          0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL10
#define MMMC_VM_MX_L1_TLS0_CNTL10__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL10__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL10__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL10__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL10__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL10__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL11
#define MMMC_VM_MX_L1_TLS0_CNTL11__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL11__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL11__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL11__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL11__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL11__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL12
#define MMMC_VM_MX_L1_TLS0_CNTL12__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL12__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL12__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL12__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL12__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL12__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL13
#define MMMC_VM_MX_L1_TLS0_CNTL13__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL13__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL13__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL13__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL13__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL13__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL14
#define MMMC_VM_MX_L1_TLS0_CNTL14__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL14__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL14__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL14__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL14__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL14__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL15
#define MMMC_VM_MX_L1_TLS0_CNTL15__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL15__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL15__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL15__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL15__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL15__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL16
#define MMMC_VM_MX_L1_TLS0_CNTL16__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL16__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL16__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL16__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL16__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL16__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL17
#define MMMC_VM_MX_L1_TLS0_CNTL17__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL17__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL17__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL17__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL17__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL17__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL18
#define MMMC_VM_MX_L1_TLS0_CNTL18__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL18__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL18__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL18__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL18__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL18__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL19
#define MMMC_VM_MX_L1_TLS0_CNTL19__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL19__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL19__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL19__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL19__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL19__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL20
#define MMMC_VM_MX_L1_TLS0_CNTL20__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL20__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL20__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL20__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL20__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL20__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL21
#define MMMC_VM_MX_L1_TLS0_CNTL21__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL21__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL21__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL21__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL21__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL21__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL22
#define MMMC_VM_MX_L1_TLS0_CNTL22__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL22__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL22__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL22__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL22__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL22__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL23
#define MMMC_VM_MX_L1_TLS0_CNTL23__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL23__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL23__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL23__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL23__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL23__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL24
#define MMMC_VM_MX_L1_TLS0_CNTL24__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL24__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL24__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL24__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL24__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL24__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL25
#define MMMC_VM_MX_L1_TLS0_CNTL25__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL25__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL25__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL25__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL25__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL25__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL26
#define MMMC_VM_MX_L1_TLS0_CNTL26__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL26__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL26__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL26__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL26__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL26__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL27
#define MMMC_VM_MX_L1_TLS0_CNTL27__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL27__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL27__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL27__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL27__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL27__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL28
#define MMMC_VM_MX_L1_TLS0_CNTL28__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL28__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL28__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL28__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL28__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL28__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL29
#define MMMC_VM_MX_L1_TLS0_CNTL29__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL29__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL29__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL29__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL29__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL29__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL30
#define MMMC_VM_MX_L1_TLS0_CNTL30__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL30__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL30__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL30__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL30__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL30__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL31
#define MMMC_VM_MX_L1_TLS0_CNTL31__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL31__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL31__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL31__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL31__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL31__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL32
#define MMMC_VM_MX_L1_TLS0_CNTL32__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL32__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL32__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL32__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL32__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL32__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL33
#define MMMC_VM_MX_L1_TLS0_CNTL33__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL33__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL33__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL33__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL33__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL33__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL34
#define MMMC_VM_MX_L1_TLS0_CNTL34__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL34__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL34__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL34__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL34__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL34__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL35
#define MMMC_VM_MX_L1_TLS0_CNTL35__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL35__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL35__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL35__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL35__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL35__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL36
#define MMMC_VM_MX_L1_TLS0_CNTL36__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL36__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL36__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL36__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL36__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL36__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_CNTL37
#define MMMC_VM_MX_L1_TLS0_CNTL37__REQ_STREAM_ID__SHIFT                                                       0x0
#define MMMC_VM_MX_L1_TLS0_CNTL37__EN__SHIFT                                                                  0xc
#define MMMC_VM_MX_L1_TLS0_CNTL37__PREFETCH_DONE__SHIFT                                                       0xd
#define MMMC_VM_MX_L1_TLS0_CNTL37__REQ_STREAM_ID_MASK                                                         0x000001FFL
#define MMMC_VM_MX_L1_TLS0_CNTL37__EN_MASK                                                                    0x00001000L
#define MMMC_VM_MX_L1_TLS0_CNTL37__PREFETCH_DONE_MASK                                                         0x00002000L
//MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32__START_ADDR_LO32__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR0_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32__START_ADDR_HI4__SHIFT                                            0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR0_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32__START_ADDR_LO32__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR1_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32__START_ADDR_HI4__SHIFT                                            0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR1_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32__START_ADDR_LO32__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR2_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32__START_ADDR_HI4__SHIFT                                            0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR2_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32__START_ADDR_LO32__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR3_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32__START_ADDR_HI4__SHIFT                                            0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR3_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32__START_ADDR_LO32__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR4_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32__START_ADDR_HI4__SHIFT                                            0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR4_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32__START_ADDR_LO32__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR5_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32__START_ADDR_HI4__SHIFT                                            0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR5_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32__START_ADDR_LO32__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR6_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32__START_ADDR_HI4__SHIFT                                            0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR6_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32__START_ADDR_LO32__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR7_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32__START_ADDR_HI4__SHIFT                                            0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR7_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32__START_ADDR_LO32__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR8_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32__START_ADDR_HI4__SHIFT                                            0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR8_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32__START_ADDR_LO32__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR9_LO32__START_ADDR_LO32_MASK                                             0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32__START_ADDR_HI4__SHIFT                                            0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR9_HI32__START_ADDR_HI4_MASK                                              0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR10_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR10_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR11_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR11_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR12_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR12_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR13_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR13_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR14_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR14_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR15_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR15_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR16_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR16_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR17_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR17_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR18_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR18_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR19_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR19_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR20_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR20_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR21_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR21_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR22_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR22_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR23_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR23_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR24_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR24_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR25_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR25_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR26_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR26_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR27_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR27_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR28_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR28_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR29_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR29_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR30_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR30_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR31_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR31_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR32_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR32_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR33_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR33_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR34_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR34_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR35_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR35_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR36_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR36_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32
#define MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32__START_ADDR_LO32__SHIFT                                          0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR37_LO32__START_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32
#define MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32__START_ADDR_HI4__SHIFT                                           0x0
#define MMMC_VM_MX_L1_TLS0_START_ADDR37_HI32__START_ADDR_HI4_MASK                                             0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32__END_ADDR_LO32__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR0_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32__END_ADDR_HI4__SHIFT                                                0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR0_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32__END_ADDR_LO32__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR1_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32__END_ADDR_HI4__SHIFT                                                0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR1_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32__END_ADDR_LO32__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR2_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32__END_ADDR_HI4__SHIFT                                                0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR2_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32__END_ADDR_LO32__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR3_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32__END_ADDR_HI4__SHIFT                                                0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR3_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32__END_ADDR_LO32__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR4_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32__END_ADDR_HI4__SHIFT                                                0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR4_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32__END_ADDR_LO32__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR5_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32__END_ADDR_HI4__SHIFT                                                0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR5_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32__END_ADDR_LO32__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR6_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32__END_ADDR_HI4__SHIFT                                                0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR6_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32__END_ADDR_LO32__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR7_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32__END_ADDR_HI4__SHIFT                                                0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR7_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32__END_ADDR_LO32__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR8_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32__END_ADDR_HI4__SHIFT                                                0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR8_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32__END_ADDR_LO32__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR9_LO32__END_ADDR_LO32_MASK                                                 0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32__END_ADDR_HI4__SHIFT                                                0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR9_HI32__END_ADDR_HI4_MASK                                                  0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR10_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR10_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR11_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR11_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR12_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR12_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR13_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR13_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR14_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR14_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR15_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR15_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR16_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR16_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR17_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR17_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR18_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR18_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR19_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR19_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR20_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR20_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR21_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR21_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR22_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR22_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR23_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR23_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR24_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR24_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR25_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR25_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR26_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR26_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR27_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR27_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR28_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR28_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR29_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR29_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR30_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR30_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR31_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR31_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR32_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR32_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR33_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR33_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR34_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR34_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR35_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR35_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR36_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR36_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32
#define MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32__END_ADDR_LO32__SHIFT                                              0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR37_LO32__END_ADDR_LO32_MASK                                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32
#define MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32__END_ADDR_HI4__SHIFT                                               0x0
#define MMMC_VM_MX_L1_TLS0_END_ADDR37_HI32__END_ADDR_HI4_MASK                                                 0x0000000FL
//MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32
#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32__INVALIDATE_STREAM_LO32__SHIFT                              0x0
#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_LO32__INVALIDATE_STREAM_LO32_MASK                                0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32
#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32__INVALIDATE_STREAM_HI6__SHIFT                               0x0
#define MMMC_VM_MX_L1_TLS0_INVALIDATE_STREAM_HI32__INVALIDATE_STREAM_HI6_MASK                                 0x0000003FL
//MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32
#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32__INVALIDATE_REQUEST_PENDING_LO32__SHIFT            0x0
#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_LO32__INVALIDATE_REQUEST_PENDING_LO32_MASK              0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32
#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32__INVALIDATE_REQUEST_PENDING_HI6__SHIFT             0x0
#define MMMC_VM_MX_L1_TLS0_INVALIDATE_REQUEST_PENDING_HI32__INVALIDATE_REQUEST_PENDING_HI6_MASK               0x0000003FL
//MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS
#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS__SHIFT                                        0x0
#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID__SHIFT                                   0xc
#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW__SHIFT                                   0x18
#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID__SHIFT                                               0x19
#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT                                             0x1d
#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__PROTECTIONS_MASK                                          0x000000FFL
#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_ID_MASK                                     0x001FF000L
#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__MEMORY_CLIENT_RW_MASK                                     0x01000000L
#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__VMID_MASK                                                 0x1E000000L
#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS__ATOMIC_MASK                                               0x20000000L
//MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32
#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                          0x0
#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                            0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32
#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                           0x0
#define MMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                             0x0000000FL
//MMVM_L2_SAW_CNTL
#define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE__SHIFT                                                              0x0
#define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT                                                0x1
#define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT                                                0x2
#define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT                                                0x4
#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT                                            0x8
#define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                      0x9
#define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                     0xa
#define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                     0xb
#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT                                                     0xc
#define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT                                                      0xf
#define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT                                                     0x12
#define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT                                                0x13
#define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT                                                  0x15
#define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT                                              0x1a
#define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT                                            0x1c
#define MMVM_L2_SAW_CNTL__ENABLE_L2_CACHE_MASK                                                                0x00000001L
#define MMVM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK                                                  0x00000002L
#define MMVM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK                                                  0x0000000CL
#define MMVM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK                                                  0x00000030L
#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK                                              0x00000100L
#define MMVM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK                                        0x00000200L
#define MMVM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK                                       0x00000400L
#define MMVM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                       0x00000800L
#define MMVM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK                                                       0x00007000L
#define MMVM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK                                                        0x00038000L
#define MMVM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION_MASK                                                       0x00040000L
#define MMVM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK                                                  0x00180000L
#define MMVM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK                                                    0x03E00000L
#define MMVM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK                                                0x0C000000L
#define MMVM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK                                              0x70000000L
//MMVM_L2_SAW_CNTL2
#define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT                                                      0x0
#define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE__SHIFT                                                         0x1
#define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT                                               0x15
#define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT                                             0x16
#define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT                                                     0x17
#define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE__SHIFT                                                       0x1a
#define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                    0x1c
#define MMVM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK                                                        0x00000001L
#define MMVM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE_MASK                                                           0x00000002L
#define MMVM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK                                                 0x00200000L
#define MMVM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK                                               0x00400000L
#define MMVM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK                                                       0x03800000L
#define MMVM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE_MASK                                                         0x0C000000L
#define MMVM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK                                                      0x70000000L
//MMVM_L2_SAW_CNTL3
#define MMVM_L2_SAW_CNTL3__BANK_SELECT__SHIFT                                                                 0x0
#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT                                                        0x6
#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                    0x8
#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                                                 0xf
#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT                                                 0x14
#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                  0x15
#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT                                                0x18
#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT                                                      0x1c
#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT                                                    0x1d
#define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT                                                        0x1e
#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT                                                   0x1f
#define MMVM_L2_SAW_CNTL3__BANK_SELECT_MASK                                                                   0x0000003FL
#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE_MASK                                                          0x000000C0L
#define MMVM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                      0x00001F00L
#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                                                   0x000F8000L
#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK                                                   0x00100000L
#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                    0x00E00000L
#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                  0x0F000000L
#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK                                                        0x10000000L
#define MMVM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK                                                      0x20000000L
#define MMVM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS_MASK                                                          0x40000000L
#define MMVM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK                                                     0x80000000L
//MMVM_L2_SAW_CNTL4
#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT                                                 0x0
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT                                       0x6
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT                                         0x7
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT                                          0x8
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT                                       0x9
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT                                         0xa
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT                                          0xb
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT                                       0xc
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT                                         0xd
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT                                          0xe
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT                                       0xf
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT                                         0x10
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT                                          0x11
#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT                                               0x12
#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK                                                   0x0000003FL
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK                                         0x00000040L
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK                                           0x00000080L
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK                                            0x00000100L
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK                                         0x00000200L
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK                                           0x00000400L
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK                                            0x00000800L
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK                                         0x00001000L
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK                                           0x00002000L
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK                                            0x00004000L
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK                                         0x00008000L
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK                                           0x00010000L
#define MMVM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK                                            0x00020000L
#define MMVM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK                                                 0x00040000L
//MMVM_L2_SAW_CONTEXT0_CNTL
#define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT                                                      0x0
#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                    0x1
#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x3
#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x4
#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                        0x6
#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                          0x7
#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0x9
#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xa
#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT                                   0xb
#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0xc
#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0xd
#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT                                  0xe
#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xf
#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0x10
#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT                                   0x11
#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                             0x12
#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                               0x13
#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT                                  0x14
#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                           0x15
#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                             0x16
#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT                                0x17
#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                               0x18
#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                            0x1c
#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                              0x1d
#define MMVM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK                                                        0x00000001L
#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK                                                      0x00000006L
#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00000008L
#define MMVM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00000010L
#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                          0x00000040L
#define MMVM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                            0x00000080L
#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000200L
#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00000400L
#define MMVM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK                                     0x00000800L
#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00001000L
#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00002000L
#define MMVM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK                                    0x00004000L
#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00008000L
#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00010000L
#define MMVM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK                                     0x00020000L
#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                               0x00040000L
#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                 0x00080000L
#define MMVM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK                                    0x00100000L
#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                             0x00200000L
#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                               0x00400000L
#define MMVM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK                                  0x00800000L
#define MMVM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                 0x0F000000L
#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                              0x10000000L
#define MMVM_L2_SAW_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                0x20000000L
//MMVM_L2_SAW_CONTEXT0_CNTL2
#define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                 0x0
#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT  0x1
#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT      0x2
#define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT              0x3
#define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT                                      0x4
#define MMVM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                   0x00000001L
#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK    0x00000002L
#define MMVM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK        0x00000004L
#define MMVM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK                0x00000008L
#define MMVM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK                                        0x00000010L
//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                      0x0
#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                        0xFFFFFFFFL
//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                       0x0
#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                         0x0000000FL
//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                        0x0
#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                          0xFFFFFFFFL
//MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                         0x0
#define MMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                           0x0000000FL
//MMVM_L2_SAW_CONTEXTS_DISABLE
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT                                                0x0
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT                                                0x1
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT                                                0x2
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT                                                0x3
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT                                                0x4
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT                                                0x5
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT                                                0x6
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT                                                0x7
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT                                                0x8
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT                                                0x9
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT                                               0xa
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT                                               0xb
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT                                               0xc
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT                                               0xd
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT                                               0xe
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT                                               0xf
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK                                                  0x00000001L
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK                                                  0x00000002L
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK                                                  0x00000004L
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK                                                  0x00000008L
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK                                                  0x00000010L
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK                                                  0x00000020L
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK                                                  0x00000040L
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK                                                  0x00000080L
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK                                                  0x00000100L
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK                                                  0x00000200L
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK                                                 0x00000400L
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK                                                 0x00000800L
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK                                                 0x00001000L
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK                                                 0x00002000L
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK                                                 0x00004000L
#define MMVM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK                                                 0x00008000L
//MMVM_L2_SAW_PIPES_BUSY_LO32
#define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32__SHIFT                                                   0x0
#define MMVM_L2_SAW_PIPES_BUSY_LO32__PIPES_BUSY_LO32_MASK                                                     0xFFFFFFFFL
//MMVM_L2_SAW_PIPES_BUSY_HI32
#define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32__SHIFT                                                   0x0
#define MMVM_L2_SAW_PIPES_BUSY_HI32__PIPES_BUSY_HI32_MASK                                                     0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS
#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__MORE_FAULTS__SHIFT                                             0x0
#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__ABORT_STATUS__SHIFT                                            0x1
#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__STREAM_ID__SHIFT                                               0x3
#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__MORE_FAULTS_MASK                                               0x00000001L
#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__ABORT_STATUS_MASK                                              0x00000006L
#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_STATUS__STREAM_ID_MASK                                                 0x000001F8L
//MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32
#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                             0x0
#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                               0xFFFFFFFFL
//MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32
#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                              0x0
#define MMMC_VM_MX_L1_TLS0_IOMMU_FAULT_GVADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                                0x0000000FL


// addressBlock: mmhub_mmutcl2_mmatcl2dec
//MM_ATC_L2_CNTL
#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT                                            0x0
#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT                                           0x3
#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                                0x6
#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                               0x7
#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT                                       0x8
#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT                                      0xb
#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT                           0xe
#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT                          0xf
#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT                                                          0x10
#define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                       0x13
#define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT                                                            0x14
#define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT                                                          0x16
#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK                                              0x00000003L
#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK                                             0x00000018L
#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                                  0x00000040L
#define MM_ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                                 0x00000080L
#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK                                         0x00000300L
#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK                                        0x00001800L
#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK                             0x00004000L
#define MM_ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK                            0x00008000L
#define MM_ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK                                                            0x00070000L
#define MM_ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                         0x00080000L
#define MM_ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK                                                              0x00300000L
#define MM_ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK                                                            0x0FC00000L
//MM_ATC_L2_CNTL2
#define MM_ATC_L2_CNTL2__BANK_SELECT__SHIFT                                                                   0x0
#define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT                                                                0x6
#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT                                                          0x9
#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                           0xb
#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT                                                  0xc
#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT                                                            0xf
#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                      0x12
#define MM_ATC_L2_CNTL2__BANK_SELECT_MASK                                                                     0x0000003FL
#define MM_ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK                                                                  0x000001C0L
#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK                                                            0x00000600L
#define MM_ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK                                             0x00000800L
#define MM_ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK                                                    0x00007000L
#define MM_ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK                                                              0x00038000L
#define MM_ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                        0x00FC0000L
//MM_ATC_L2_CACHE_DATA0
#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT                                                     0x0
#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT                                                       0x1
#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT                                                       0x2
#define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT                                               0x18
#define MM_ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK                                                       0x00000001L
#define MM_ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK                                                         0x00000002L
#define MM_ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK                                                         0x00FFFFFCL
#define MM_ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK                                                 0x0F000000L
//MM_ATC_L2_CACHE_DATA1
#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT                                                0x0
#define MM_ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK                                                  0xFFFFFFFFL
//MM_ATC_L2_CACHE_DATA2
#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT                                                   0x0
#define MM_ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK                                                     0xFFFFFFFFL
//MM_ATC_L2_CNTL3
#define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT                                                 0x0
#define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE__SHIFT                                                   0x6
#define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE__SHIFT                                                   0xc
#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT                                               0x12
#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT                                                     0x15
#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT                                                     0x1b
#define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT                                                             0x1e
#define MM_ATC_L2_CNTL3__L2_SMALLK_CACHE_FRAGMENT_SIZE_MASK                                                   0x0000003FL
#define MM_ATC_L2_CNTL3__L2_MIDK_CACHE_FRAGMENT_SIZE_MASK                                                     0x00000FC0L
#define MM_ATC_L2_CNTL3__L2_BIGK_CACHE_FRAGMENT_SIZE_MASK                                                     0x0003F000L
#define MM_ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK                                                 0x001C0000L
#define MM_ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK                                                       0x07E00000L
#define MM_ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK                                                       0x38000000L
#define MM_ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK                                                               0x40000000L
//MM_ATC_L2_CNTL4
#define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE__SHIFT                                              0x0
#define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE__SHIFT                                                0x6
#define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE__SHIFT                                                0xc
#define MM_ATC_L2_CNTL4__L2_RT_SMALLK_CACHE_FRAGMENT_SIZE_MASK                                                0x0000003FL
#define MM_ATC_L2_CNTL4__L2_RT_MIDK_CACHE_FRAGMENT_SIZE_MASK                                                  0x00000FC0L
#define MM_ATC_L2_CNTL4__L2_RT_BIGK_CACHE_FRAGMENT_SIZE_MASK                                                  0x0003F000L
//MM_ATC_L2_CNTL5
#define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                       0x0
#define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                      0xa
#define MM_ATC_L2_CNTL5__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                         0x000003FFL
#define MM_ATC_L2_CNTL5__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                        0x000FFC00L
//MM_ATC_L2_MM_GROUP_RT_CLASSES
#define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT                                                  0x0
#define MM_ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK                                                    0xFFFFFFFFL
//MM_ATC_L2_STATUS
#define MM_ATC_L2_STATUS__BUSY__SHIFT                                                                         0x0
#define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS__SHIFT                                                   0x1
#define MM_ATC_L2_STATUS__BUSY_MASK                                                                           0x00000001L
#define MM_ATC_L2_STATUS__NO_OUTSTANDING_AT_REQUESTS_MASK                                                     0x00000002L
//MM_ATC_L2_STATUS2
#define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT                                           0x0
#define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT                                               0x8
#define MM_ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK                                             0x000000FFL
#define MM_ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK                                                 0x0000FF00L
//MM_ATC_L2_MISC_CG
#define MM_ATC_L2_MISC_CG__OFFDLY__SHIFT                                                                      0x6
#define MM_ATC_L2_MISC_CG__ENABLE__SHIFT                                                                      0x12
#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT                                                               0x13
#define MM_ATC_L2_MISC_CG__OFFDLY_MASK                                                                        0x00000FC0L
#define MM_ATC_L2_MISC_CG__ENABLE_MASK                                                                        0x00040000L
#define MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK                                                                 0x00080000L
//MM_ATC_L2_MEM_POWER_LS
#define MM_ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT                                                               0x0
#define MM_ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT                                                                0x6
#define MM_ATC_L2_MEM_POWER_LS__LS_SETUP_MASK                                                                 0x0000003FL
#define MM_ATC_L2_MEM_POWER_LS__LS_HOLD_MASK                                                                  0x00000FC0L
//MM_ATC_L2_CGTT_CLK_CTRL
#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                              0x0
#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                        0x5
#define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT                                                  0xd
#define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT                                                            0x1e
#define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT                                                         0x1f
#define MM_ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                0x0000001FL
#define MM_ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                          0x00001FE0L
#define MM_ATC_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK                                                    0x1FFFE000L
#define MM_ATC_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK                                                              0x40000000L
#define MM_ATC_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK                                                           0x80000000L
//MM_ATC_L2_SDPPORT_CTRL
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN__SHIFT                                                      0x0
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV__SHIFT                                                   0x1
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN__SHIFT                                                  0x2
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV__SHIFT                                               0x3
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN__SHIFT                                                      0x4
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV__SHIFT                                                   0x5
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN__SHIFT                                                        0x6
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV__SHIFT                                                     0x7
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN__SHIFT                                                   0x8
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV__SHIFT                                                0x9
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKEN_MASK                                                        0x00000001L
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPCKENRCV_MASK                                                     0x00000002L
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKEN_MASK                                                    0x00000004L
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_RDRSPDATACKENRCV_MASK                                                 0x00000008L
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKEN_MASK                                                        0x00000010L
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_WRRSPCKENRCV_MASK                                                     0x00000020L
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKEN_MASK                                                          0x00000040L
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_REQCKENRCV_MASK                                                       0x00000080L
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKEN_MASK                                                     0x00000100L
#define MM_ATC_L2_SDPPORT_CTRL__SDPVDCI_ORIGDATACKENRCV_MASK                                                  0x00000200L


// addressBlock: mmhub_mmutcl2_mmvml2pfdec
//MMVM_L2_CNTL
#define MMVM_L2_CNTL__ENABLE_L2_CACHE__SHIFT                                                                  0x0
#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT                                                    0x1
#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT                                                    0x2
#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT                                                    0x4
#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT                                                0x8
#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                          0x9
#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT                                         0xa
#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT                                         0xb
#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT                                                         0xc
#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT                                                          0xf
#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT                                                         0x12
#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT                                                    0x13
#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT                                                      0x15
#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT                                                           0x1a
#define MMVM_L2_CNTL__ENABLE_L2_CACHE_MASK                                                                    0x00000001L
#define MMVM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK                                                      0x00000002L
#define MMVM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK                                                      0x0000000CL
#define MMVM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK                                                      0x00000030L
#define MMVM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK                                                  0x00000100L
#define MMVM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK                                            0x00000200L
#define MMVM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK                                           0x00000400L
#define MMVM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK                                           0x00000800L
#define MMVM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK                                                           0x00007000L
#define MMVM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK                                                            0x00038000L
#define MMVM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK                                                           0x00040000L
#define MMVM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK                                                      0x00180000L
#define MMVM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK                                                        0x03E00000L
#define MMVM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK                                                             0x0C000000L
//MMVM_L2_CNTL2
#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT                                                          0x0
#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT                                                             0x1
#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT                                                   0x15
#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT                                                 0x16
#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT                                                          0x17
#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT                                                           0x1a
#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT                                                        0x1c
#define MMVM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK                                                            0x00000001L
#define MMVM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK                                                               0x00000002L
#define MMVM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK                                                     0x00200000L
#define MMVM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK                                                   0x00400000L
#define MMVM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK                                                            0x03800000L
#define MMVM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK                                                             0x0C000000L
#define MMVM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK                                                          0x70000000L
//MMVM_L2_CNTL3
#define MMVM_L2_CNTL3__BANK_SELECT__SHIFT                                                                     0x0
#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT                                                            0x6
#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT                                        0x8
#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                                                     0xf
#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT                                                     0x14
#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT                                                      0x15
#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT                                                    0x18
#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT                                                          0x1c
#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT                                                        0x1d
#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT                                                            0x1e
#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT                                                       0x1f
#define MMVM_L2_CNTL3__BANK_SELECT_MASK                                                                       0x0000003FL
#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK                                                              0x000000C0L
#define MMVM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK                                          0x00001F00L
#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                                                       0x000F8000L
#define MMVM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK                                                       0x00100000L
#define MMVM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK                                                        0x00E00000L
#define MMVM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK                                                      0x0F000000L
#define MMVM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK                                                            0x10000000L
#define MMVM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK                                                          0x20000000L
#define MMVM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK                                                              0x40000000L
#define MMVM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK                                                         0x80000000L
//MMVM_L2_STATUS
#define MMVM_L2_STATUS__L2_BUSY__SHIFT                                                                        0x0
#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT                                                            0x1
#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT                                               0x11
#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT                                             0x12
#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT                                                 0x13
#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT                                                 0x14
#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT                                                 0x15
#define MMVM_L2_STATUS__L2_BUSY_MASK                                                                          0x00000001L
#define MMVM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK                                                              0x0001FFFEL
#define MMVM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK                                                 0x00020000L
#define MMVM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK                                               0x00040000L
#define MMVM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK                                                   0x00080000L
#define MMVM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK                                                   0x00100000L
#define MMVM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK                                                   0x00200000L
//MMVM_DUMMY_PAGE_FAULT_CNTL
#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT                                            0x0
#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT                                         0x1
#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT                                            0x2
#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK                                              0x00000001L
#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK                                           0x00000002L
#define MMVM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK                                              0x000000FCL
//MMVM_DUMMY_PAGE_FAULT_ADDR_LO32
#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT                                          0x0
#define MMVM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK                                            0xFFFFFFFFL
//MMVM_DUMMY_PAGE_FAULT_ADDR_HI32
#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT                                           0x0
#define MMVM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK                                             0x0000000FL
//MMVM_INVALIDATE_CNTL
#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING__SHIFT                                                      0x0
#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING__SHIFT                                                      0x8
#define MMVM_INVALIDATE_CNTL__PRI_REG_ALTERNATING_MASK                                                        0x000000FFL
#define MMVM_INVALIDATE_CNTL__MAX_REG_OUTSTANDING_MASK                                                        0x0000FF00L
//MMVM_L2_PROTECTION_FAULT_CNTL
#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                              0x0
#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT           0x1
#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0x2
#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x3
#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x4
#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x5
#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT               0x6
#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0x7
#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                      0x8
#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0x9
#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                            0xa
#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                           0xb
#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                         0xc
#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                              0xd
#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                        0x1d
#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT                                         0x1e
#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT                                            0x1f
#define MMVM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                0x00000001L
#define MMVM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK             0x00000002L
#define MMVM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00000004L
#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000008L
#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000010L
#define MMVM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000020L
#define MMVM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                 0x00000040L
#define MMVM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000080L
#define MMVM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                        0x00000100L
#define MMVM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00000200L
#define MMVM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                              0x00000400L
#define MMVM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                             0x00000800L
#define MMVM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                           0x00001000L
#define MMVM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                                0x1FFFE000L
#define MMVM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                          0x20000000L
#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK                                           0x40000000L
#define MMVM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK                                              0x80000000L
//MMVM_L2_PROTECTION_FAULT_CNTL2
#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                                  0x0
#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT                            0x10
#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT                                      0x11
#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT                           0x12
#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT                                   0x13
#define MMVM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                                    0x0000FFFFL
#define MMVM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK                              0x00010000L
#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK                                        0x00020000L
#define MMVM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK                             0x00040000L
#define MMVM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK                                     0x00080000L
//MMVM_L2_PROTECTION_FAULT_MM_CNTL3
#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT                0x0
#define MMVM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                  0xFFFFFFFFL
//MMVM_L2_PROTECTION_FAULT_MM_CNTL4
#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT               0x0
#define MMVM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK                 0xFFFFFFFFL
//MMVM_L2_PROTECTION_FAULT_STATUS
#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT                                                   0x0
#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT                                                  0x1
#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT                                             0x4
#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT                                                 0x8
#define MMVM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT                                                           0x9
#define MMVM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT                                                            0x12
#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT                                                        0x13
#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT                                                          0x14
#define MMVM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT                                                            0x18
#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT                                                          0x19
#define MMVM_L2_PROTECTION_FAULT_STATUS__PRT__SHIFT                                                           0x1d
#define MMVM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK                                                     0x00000001L
#define MMVM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK                                                    0x0000000EL
#define MMVM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK                                               0x000000F0L
#define MMVM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK                                                   0x00000100L
#define MMVM_L2_PROTECTION_FAULT_STATUS__CID_MASK                                                             0x0003FE00L
#define MMVM_L2_PROTECTION_FAULT_STATUS__RW_MASK                                                              0x00040000L
#define MMVM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK                                                          0x00080000L
#define MMVM_L2_PROTECTION_FAULT_STATUS__VMID_MASK                                                            0x00F00000L
#define MMVM_L2_PROTECTION_FAULT_STATUS__VF_MASK                                                              0x01000000L
#define MMVM_L2_PROTECTION_FAULT_STATUS__VFID_MASK                                                            0x1E000000L
#define MMVM_L2_PROTECTION_FAULT_STATUS__PRT_MASK                                                             0x20000000L
//MMVM_L2_PROTECTION_FAULT_ADDR_LO32
#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT                                     0x0
#define MMVM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK                                       0xFFFFFFFFL
//MMVM_L2_PROTECTION_FAULT_ADDR_HI32
#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT                                      0x0
#define MMVM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK                                        0x0000000FL
//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32
#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT                            0x0
#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK                              0xFFFFFFFFL
//MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32
#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT                             0x0
#define MMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK                               0x0000000FL
//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32
#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                     0x0
#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                       0xFFFFFFFFL
//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32
#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                      0x0
#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                        0x0000000FL
//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32
#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                    0x0
#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                      0xFFFFFFFFL
//MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32
#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                     0x0
#define MMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                       0x0000000FL
//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32
#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT                       0x0
#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK                         0xFFFFFFFFL
//MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32
#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT                        0x0
#define MMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK                          0x0000000FL
//MMVM_L2_CNTL4
#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT                                                     0x0
#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT                                                    0x6
#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT                                                    0x7
#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                         0x8
#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT                                        0x12
#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT                                                             0x1c
#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT                                                                  0x1d
#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT                                                             0x1e
#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS__SHIFT                                                        0x1f
#define MMVM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK                                                       0x0000003FL
#define MMVM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK                                                      0x00000040L
#define MMVM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK                                                      0x00000080L
#define MMVM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                           0x0003FF00L
#define MMVM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK                                          0x0FFC0000L
#define MMVM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK                                                               0x10000000L
#define MMVM_L2_CNTL4__GC_CH_FGCG_OFF_MASK                                                                    0x20000000L
#define MMVM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK                                                               0x40000000L
#define MMVM_L2_CNTL4__VFIFO_VISIBLE_BANK_SILOS_MASK                                                          0x80000000L
//MMVM_L2_MM_GROUP_RT_CLASSES
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT                                                  0x0
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT                                                  0x1
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT                                                  0x2
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT                                                  0x3
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT                                                  0x4
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT                                                  0x5
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT                                                  0x6
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT                                                  0x7
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT                                                  0x8
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT                                                  0x9
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT                                                 0xa
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT                                                 0xb
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT                                                 0xc
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT                                                 0xd
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT                                                 0xe
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT                                                 0xf
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT                                                 0x10
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT                                                 0x11
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT                                                 0x12
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT                                                 0x13
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT                                                 0x14
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT                                                 0x15
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT                                                 0x16
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT                                                 0x17
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT                                                 0x18
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT                                                 0x19
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT                                                 0x1a
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT                                                 0x1b
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT                                                 0x1c
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT                                                 0x1d
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT                                                 0x1e
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT                                                 0x1f
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK                                                    0x00000001L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK                                                    0x00000002L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK                                                    0x00000004L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK                                                    0x00000008L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK                                                    0x00000010L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK                                                    0x00000020L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK                                                    0x00000040L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK                                                    0x00000080L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK                                                    0x00000100L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK                                                    0x00000200L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK                                                   0x00000400L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK                                                   0x00000800L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK                                                   0x00001000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK                                                   0x00002000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK                                                   0x00004000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK                                                   0x00008000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK                                                   0x00010000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK                                                   0x00020000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK                                                   0x00040000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK                                                   0x00080000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK                                                   0x00100000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK                                                   0x00200000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK                                                   0x00400000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK                                                   0x00800000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK                                                   0x01000000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK                                                   0x02000000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK                                                   0x04000000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK                                                   0x08000000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK                                                   0x10000000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK                                                   0x20000000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK                                                   0x40000000L
#define MMVM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK                                                   0x80000000L
//MMVM_L2_BANK_SELECT_RESERVED_CID
#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT                                      0x0
#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT                                     0xa
#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT                                                       0x14
#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                             0x18
#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                          0x19
#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT                                 0x1a
#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK                                        0x000001FFL
#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK                                       0x0007FC00L
#define MMVM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK                                                         0x00100000L
#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK                               0x01000000L
#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                            0x02000000L
#define MMVM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_FRAGMENT_SIZE_MASK                                   0x7C000000L
//MMVM_L2_BANK_SELECT_RESERVED_CID2
#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT                                     0x0
#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT                                    0xa
#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT                                                      0x14
#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT                            0x18
#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT                         0x19
#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE__SHIFT                                0x1a
#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK                                       0x000001FFL
#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK                                      0x0007FC00L
#define MMVM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK                                                        0x00100000L
#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK                              0x01000000L
#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK                           0x02000000L
#define MMVM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_FRAGMENT_SIZE_MASK                                  0x7C000000L
//MMVM_L2_CACHE_PARITY_CNTL
#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT                               0x0
#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT                             0x1
#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT                                  0x2
#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT                               0x3
#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT                             0x4
#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT                                  0x5
#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT                                                    0x6
#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT                                                  0x9
#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT                                                   0xc
#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK                                 0x00000001L
#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK                               0x00000002L
#define MMVM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK                                    0x00000004L
#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK                                 0x00000008L
#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK                               0x00000010L
#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK                                    0x00000020L
#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK                                                      0x000001C0L
#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK                                                    0x00000E00L
#define MMVM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK                                                     0x0000F000L
//MMVM_L2_CGTT_CLK_CTRL
#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                0x0
#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                          0x5
#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT                                                    0xd
#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT                                                              0x1e
#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT                                                           0x1f
#define MMVM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                  0x0000001FL
#define MMVM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                            0x00001FE0L
#define MMVM_L2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK                                                      0x1FFFE000L
#define MMVM_L2_CGTT_CLK_CTRL__LS_DISABLE_MASK                                                                0x40000000L
#define MMVM_L2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK                                                             0x80000000L
//MMVM_L2_CNTL5
#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT                                                   0x0
#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID__SHIFT                                                       0x5
#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE__SHIFT                                                 0xe
#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE__SHIFT                                                   0xf
#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF__SHIFT                                                          0x10
#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF__SHIFT                                                          0x11
#define MMVM_L2_CNTL5__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                                                     0x0000001FL
#define MMVM_L2_CNTL5__WALKER_PRIORITY_CLIENT_ID_MASK                                                         0x00003FE0L
#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_NOALLOC_ENABLE_MASK                                                   0x00004000L
#define MMVM_L2_CNTL5__WALKER_FETCH_PDE_MTYPE_ENABLE_MASK                                                     0x00008000L
#define MMVM_L2_CNTL5__MM_CLIENT_RET_FGCG_OFF_MASK                                                            0x00010000L
#define MMVM_L2_CNTL5__UTCL2_ATC_REQ_FGCG_OFF_MASK                                                            0x00020000L
//MMVM_L2_GCR_CNTL
#define MMVM_L2_GCR_CNTL__GCR_ENABLE__SHIFT                                                                   0x0
#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID__SHIFT                                                                0x1
#define MMVM_L2_GCR_CNTL__GCR_ENABLE_MASK                                                                     0x00000001L
#define MMVM_L2_GCR_CNTL__GCR_CLIENT_ID_MASK                                                                  0x000003FEL
//MMVM_L2_CGTT_BUSY_CTRL
#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT                                                             0x0
#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT                                                            0x5
#define MMVM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK                                                               0x0000001FL
#define MMVM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK                                                              0x00000020L
//MMVM_L2_PTE_CACHE_DUMP_CNTL
#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE__SHIFT                                                            0x0
#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY__SHIFT                                                             0x1
#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK__SHIFT                                                              0x4
#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE__SHIFT                                                             0x8
#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC__SHIFT                                                             0xc
#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX__SHIFT                                                             0x10
#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ENABLE_MASK                                                              0x00000001L
#define MMVM_L2_PTE_CACHE_DUMP_CNTL__READY_MASK                                                               0x00000002L
#define MMVM_L2_PTE_CACHE_DUMP_CNTL__BANK_MASK                                                                0x000000F0L
#define MMVM_L2_PTE_CACHE_DUMP_CNTL__CACHE_MASK                                                               0x00000F00L
#define MMVM_L2_PTE_CACHE_DUMP_CNTL__ASSOC_MASK                                                               0x0000F000L
#define MMVM_L2_PTE_CACHE_DUMP_CNTL__INDEX_MASK                                                               0xFFFF0000L
//MMVM_L2_PTE_CACHE_DUMP_READ
#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA__SHIFT                                                              0x0
#define MMVM_L2_PTE_CACHE_DUMP_READ__DATA_MASK                                                                0xFFFFFFFFL
//MMVM_L2_BANK_SELECT_MASKS
#define MMVM_L2_BANK_SELECT_MASKS__MASK0__SHIFT                                                               0x0
#define MMVM_L2_BANK_SELECT_MASKS__MASK1__SHIFT                                                               0x4
#define MMVM_L2_BANK_SELECT_MASKS__MASK2__SHIFT                                                               0x8
#define MMVM_L2_BANK_SELECT_MASKS__MASK3__SHIFT                                                               0xc
#define MMVM_L2_BANK_SELECT_MASKS__MASK0_MASK                                                                 0x0000000FL
#define MMVM_L2_BANK_SELECT_MASKS__MASK1_MASK                                                                 0x000000F0L
#define MMVM_L2_BANK_SELECT_MASKS__MASK2_MASK                                                                 0x00000F00L
#define MMVM_L2_BANK_SELECT_MASKS__MASK3_MASK                                                                 0x0000F000L
//MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC
#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS__SHIFT                                                   0x0
#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE__SHIFT                                                    0xa
#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__CREDITS_MASK                                                     0x000003FFL
#define MMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC__UPDATE_MASK                                                      0x00000400L
//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC
#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS__SHIFT                                        0x0
#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE__SHIFT                                         0xa
#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__CREDITS_MASK                                          0x000003FFL
#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC__UPDATE_MASK                                           0x00000400L
//MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC
#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS__SHIFT                                      0x0
#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE__SHIFT                                       0xa
#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__CREDITS_MASK                                        0x000003FFL
#define MMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC__UPDATE_MASK                                         0x00000400L
//MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT
#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS__SHIFT                                               0x0
#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE__SHIFT                                                0xa
#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__CREDITS_MASK                                                 0x000003FFL
#define MMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT__UPDATE_MASK                                                  0x00000400L
//MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ
#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT                                               0x0
#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE__SHIFT                                                0xa
#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK                                                 0x000003FFL
#define MMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ__UPDATE_MASK                                                  0x00000400L


// addressBlock: mmhub_mmutcl2_mmvml2vcdec
//MMVM_CONTEXT0_CNTL
#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
#define MMVM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define MMVM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define MMVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define MMVM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define MMVM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define MMVM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define MMVM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define MMVM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define MMVM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define MMVM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define MMVM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
#define MMVM_CONTEXT0_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
//MMVM_CONTEXT1_CNTL
#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
#define MMVM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define MMVM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define MMVM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define MMVM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
#define MMVM_CONTEXT1_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
//MMVM_CONTEXT2_CNTL
#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
#define MMVM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define MMVM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define MMVM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define MMVM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define MMVM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define MMVM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define MMVM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define MMVM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define MMVM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define MMVM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define MMVM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
#define MMVM_CONTEXT2_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
//MMVM_CONTEXT3_CNTL
#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
#define MMVM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define MMVM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define MMVM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define MMVM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define MMVM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define MMVM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define MMVM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define MMVM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define MMVM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define MMVM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define MMVM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
#define MMVM_CONTEXT3_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
//MMVM_CONTEXT4_CNTL
#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
#define MMVM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define MMVM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define MMVM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define MMVM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define MMVM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define MMVM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define MMVM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define MMVM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define MMVM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define MMVM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define MMVM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
#define MMVM_CONTEXT4_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
//MMVM_CONTEXT5_CNTL
#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
#define MMVM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define MMVM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define MMVM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define MMVM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define MMVM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define MMVM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define MMVM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define MMVM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define MMVM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define MMVM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define MMVM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
#define MMVM_CONTEXT5_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
//MMVM_CONTEXT6_CNTL
#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
#define MMVM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define MMVM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define MMVM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define MMVM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define MMVM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define MMVM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define MMVM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define MMVM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define MMVM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define MMVM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define MMVM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
#define MMVM_CONTEXT6_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
//MMVM_CONTEXT7_CNTL
#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
#define MMVM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define MMVM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define MMVM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define MMVM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define MMVM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define MMVM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define MMVM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define MMVM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define MMVM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define MMVM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define MMVM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
#define MMVM_CONTEXT7_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
//MMVM_CONTEXT8_CNTL
#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
#define MMVM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define MMVM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define MMVM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define MMVM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define MMVM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define MMVM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define MMVM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define MMVM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define MMVM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define MMVM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define MMVM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
#define MMVM_CONTEXT8_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
//MMVM_CONTEXT9_CNTL
#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT                                                             0x0
#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                           0x1
#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                      0x3
#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                     0x7
#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT                                                          0x8
#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x9
#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xa
#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                               0xb
#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                 0xc
#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0xd
#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0xe
#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xf
#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x10
#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                     0x11
#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                       0x12
#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x13
#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x14
#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x15
#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x16
#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x17
#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x18
#define MMVM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK                                                               0x00000001L
#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK                                                             0x00000006L
#define MMVM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                        0x00000078L
#define MMVM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                       0x00000080L
#define MMVM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK                                                            0x00000100L
#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00000200L
#define MMVM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00000400L
#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                 0x00000800L
#define MMVM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                   0x00001000L
#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00002000L
#define MMVM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00004000L
#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00008000L
#define MMVM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00010000L
#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                       0x00020000L
#define MMVM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                         0x00040000L
#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00080000L
#define MMVM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00100000L
#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00200000L
#define MMVM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x00400000L
#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00800000L
#define MMVM_CONTEXT9_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x01000000L
//MMVM_CONTEXT10_CNTL
#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
#define MMVM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
#define MMVM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
#define MMVM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
#define MMVM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
#define MMVM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
#define MMVM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
#define MMVM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
#define MMVM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
#define MMVM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
#define MMVM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
#define MMVM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
#define MMVM_CONTEXT10_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
//MMVM_CONTEXT11_CNTL
#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
#define MMVM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
#define MMVM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
#define MMVM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
#define MMVM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
#define MMVM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
#define MMVM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
#define MMVM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
#define MMVM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
#define MMVM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
#define MMVM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
#define MMVM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
#define MMVM_CONTEXT11_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
//MMVM_CONTEXT12_CNTL
#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
#define MMVM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
#define MMVM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
#define MMVM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
#define MMVM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
#define MMVM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
#define MMVM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
#define MMVM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
#define MMVM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
#define MMVM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
#define MMVM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
#define MMVM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
#define MMVM_CONTEXT12_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
//MMVM_CONTEXT13_CNTL
#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
#define MMVM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
#define MMVM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
#define MMVM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
#define MMVM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
#define MMVM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
#define MMVM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
#define MMVM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
#define MMVM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
#define MMVM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
#define MMVM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
#define MMVM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
#define MMVM_CONTEXT13_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
//MMVM_CONTEXT14_CNTL
#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
#define MMVM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
#define MMVM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
#define MMVM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
#define MMVM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
#define MMVM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
#define MMVM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
#define MMVM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
#define MMVM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
#define MMVM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
#define MMVM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
#define MMVM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
#define MMVM_CONTEXT14_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
//MMVM_CONTEXT15_CNTL
#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT                                                            0x0
#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT                                                          0x1
#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT                                                     0x3
#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT                                    0x7
#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT                                                         0x8
#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x9
#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0xa
#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                              0xb
#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                0xc
#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0xd
#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0xe
#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0xf
#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x10
#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                    0x11
#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                      0x12
#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                   0x13
#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                     0x14
#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                 0x15
#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                   0x16
#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT                                  0x17
#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT                                    0x18
#define MMVM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK                                                              0x00000001L
#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK                                                            0x00000006L
#define MMVM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK                                                       0x00000078L
#define MMVM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK                                      0x00000080L
#define MMVM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK                                                           0x00000100L
#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00000200L
#define MMVM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00000400L
#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                0x00000800L
#define MMVM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                  0x00001000L
#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00002000L
#define MMVM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00004000L
#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00008000L
#define MMVM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00010000L
#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                      0x00020000L
#define MMVM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                        0x00040000L
#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                     0x00080000L
#define MMVM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                       0x00100000L
#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                   0x00200000L
#define MMVM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                     0x00400000L
#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK                                    0x00800000L
#define MMVM_CONTEXT15_CNTL__SECURE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK                                      0x01000000L
//MMVM_CONTEXTS_DISABLE
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT                                                       0x0
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT                                                       0x1
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT                                                       0x2
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT                                                       0x3
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT                                                       0x4
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT                                                       0x5
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT                                                       0x6
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT                                                       0x7
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT                                                       0x8
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT                                                       0x9
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT                                                      0xa
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT                                                      0xb
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT                                                      0xc
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT                                                      0xd
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT                                                      0xe
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT                                                      0xf
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK                                                         0x00000001L
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK                                                         0x00000002L
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK                                                         0x00000004L
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK                                                         0x00000008L
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK                                                         0x00000010L
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK                                                         0x00000020L
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK                                                         0x00000040L
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK                                                         0x00000080L
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK                                                         0x00000100L
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK                                                         0x00000200L
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK                                                        0x00000400L
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK                                                        0x00000800L
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK                                                        0x00001000L
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK                                                        0x00002000L
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK                                                        0x00004000L
#define MMVM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK                                                        0x00008000L
//MMVM_INVALIDATE_ENG0_SEM
#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT                                                            0x0
#define MMVM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK                                                              0x00000001L
//MMVM_INVALIDATE_ENG1_SEM
#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT                                                            0x0
#define MMVM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK                                                              0x00000001L
//MMVM_INVALIDATE_ENG2_SEM
#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT                                                            0x0
#define MMVM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK                                                              0x00000001L
//MMVM_INVALIDATE_ENG3_SEM
#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT                                                            0x0
#define MMVM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK                                                              0x00000001L
//MMVM_INVALIDATE_ENG4_SEM
#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT                                                            0x0
#define MMVM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK                                                              0x00000001L
//MMVM_INVALIDATE_ENG5_SEM
#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT                                                            0x0
#define MMVM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK                                                              0x00000001L
//MMVM_INVALIDATE_ENG6_SEM
#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT                                                            0x0
#define MMVM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK                                                              0x00000001L
//MMVM_INVALIDATE_ENG7_SEM
#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT                                                            0x0
#define MMVM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK                                                              0x00000001L
//MMVM_INVALIDATE_ENG8_SEM
#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT                                                            0x0
#define MMVM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK                                                              0x00000001L
//MMVM_INVALIDATE_ENG9_SEM
#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT                                                            0x0
#define MMVM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK                                                              0x00000001L
//MMVM_INVALIDATE_ENG10_SEM
#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT                                                           0x0
#define MMVM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK                                                             0x00000001L
//MMVM_INVALIDATE_ENG11_SEM
#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT                                                           0x0
#define MMVM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK                                                             0x00000001L
//MMVM_INVALIDATE_ENG12_SEM
#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT                                                           0x0
#define MMVM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK                                                             0x00000001L
//MMVM_INVALIDATE_ENG13_SEM
#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT                                                           0x0
#define MMVM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK                                                             0x00000001L
//MMVM_INVALIDATE_ENG14_SEM
#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT                                                           0x0
#define MMVM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK                                                             0x00000001L
//MMVM_INVALIDATE_ENG15_SEM
#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT                                                           0x0
#define MMVM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK                                                             0x00000001L
//MMVM_INVALIDATE_ENG16_SEM
#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT                                                           0x0
#define MMVM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK                                                             0x00000001L
//MMVM_INVALIDATE_ENG17_SEM
#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT                                                           0x0
#define MMVM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK                                                             0x00000001L
//MMVM_INVALIDATE_ENG0_REQ
#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define MMVM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define MMVM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define MMVM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define MMVM_INVALIDATE_ENG0_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//MMVM_INVALIDATE_ENG1_REQ
#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define MMVM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define MMVM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define MMVM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define MMVM_INVALIDATE_ENG1_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//MMVM_INVALIDATE_ENG2_REQ
#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define MMVM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define MMVM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define MMVM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define MMVM_INVALIDATE_ENG2_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//MMVM_INVALIDATE_ENG3_REQ
#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define MMVM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define MMVM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define MMVM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define MMVM_INVALIDATE_ENG3_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//MMVM_INVALIDATE_ENG4_REQ
#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define MMVM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define MMVM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define MMVM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define MMVM_INVALIDATE_ENG4_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//MMVM_INVALIDATE_ENG5_REQ
#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define MMVM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define MMVM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define MMVM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define MMVM_INVALIDATE_ENG5_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//MMVM_INVALIDATE_ENG6_REQ
#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define MMVM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define MMVM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define MMVM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define MMVM_INVALIDATE_ENG6_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//MMVM_INVALIDATE_ENG7_REQ
#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define MMVM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define MMVM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define MMVM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define MMVM_INVALIDATE_ENG7_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//MMVM_INVALIDATE_ENG8_REQ
#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define MMVM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define MMVM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define MMVM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define MMVM_INVALIDATE_ENG8_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//MMVM_INVALIDATE_ENG9_REQ
#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT                                                   0x13
#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT                                                   0x14
#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT                                                   0x15
#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT                                                   0x16
#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT                                                   0x17
#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                   0x18
#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT                                                          0x19
#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                             0x1a
#define MMVM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK                                                             0x00070000L
#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK                                                     0x00080000L
#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK                                                     0x00100000L
#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK                                                     0x00200000L
#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK                                                     0x00400000L
#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK                                                     0x00800000L
#define MMVM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                     0x01000000L
#define MMVM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK                                                            0x02000000L
#define MMVM_INVALIDATE_ENG9_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                               0x04000000L
//MMVM_INVALIDATE_ENG10_REQ
#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT                                                          0x10
#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT                                                         0x19
#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
#define MMVM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
#define MMVM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
#define MMVM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
#define MMVM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK                                                           0x02000000L
#define MMVM_INVALIDATE_ENG10_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
//MMVM_INVALIDATE_ENG11_REQ
#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT                                                          0x10
#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT                                                         0x19
#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
#define MMVM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
#define MMVM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
#define MMVM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
#define MMVM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK                                                           0x02000000L
#define MMVM_INVALIDATE_ENG11_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
//MMVM_INVALIDATE_ENG12_REQ
#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT                                                          0x10
#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT                                                         0x19
#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
#define MMVM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
#define MMVM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
#define MMVM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
#define MMVM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK                                                           0x02000000L
#define MMVM_INVALIDATE_ENG12_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
//MMVM_INVALIDATE_ENG13_REQ
#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT                                                          0x10
#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT                                                         0x19
#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
#define MMVM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
#define MMVM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
#define MMVM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
#define MMVM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK                                                           0x02000000L
#define MMVM_INVALIDATE_ENG13_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
//MMVM_INVALIDATE_ENG14_REQ
#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT                                                          0x10
#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT                                                         0x19
#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
#define MMVM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
#define MMVM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
#define MMVM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
#define MMVM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK                                                           0x02000000L
#define MMVM_INVALIDATE_ENG14_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
//MMVM_INVALIDATE_ENG15_REQ
#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT                                                          0x10
#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT                                                         0x19
#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
#define MMVM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
#define MMVM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
#define MMVM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
#define MMVM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK                                                           0x02000000L
#define MMVM_INVALIDATE_ENG15_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
//MMVM_INVALIDATE_ENG16_REQ
#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT                                                          0x10
#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT                                                         0x19
#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
#define MMVM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
#define MMVM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
#define MMVM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
#define MMVM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK                                                           0x02000000L
#define MMVM_INVALIDATE_ENG16_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
//MMVM_INVALIDATE_ENG17_REQ
#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT                                             0x0
#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT                                                          0x10
#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT                                                  0x13
#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT                                                  0x14
#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT                                                  0x15
#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT                                                  0x16
#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT                                                  0x17
#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT                                  0x18
#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT                                                         0x19
#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY__SHIFT                                            0x1a
#define MMVM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK                                               0x0000FFFFL
#define MMVM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK                                                            0x00070000L
#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK                                                    0x00080000L
#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK                                                    0x00100000L
#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK                                                    0x00200000L
#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK                                                    0x00400000L
#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK                                                    0x00800000L
#define MMVM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK                                    0x01000000L
#define MMVM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK                                                           0x02000000L
#define MMVM_INVALIDATE_ENG17_REQ__INVALIDATE_4K_PAGES_ONLY_MASK                                              0x04000000L
//MMVM_INVALIDATE_ENG0_ACK
#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT                                                            0x10
#define MMVM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK                                                              0x00010000L
//MMVM_INVALIDATE_ENG1_ACK
#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT                                                            0x10
#define MMVM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK                                                              0x00010000L
//MMVM_INVALIDATE_ENG2_ACK
#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT                                                            0x10
#define MMVM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK                                                              0x00010000L
//MMVM_INVALIDATE_ENG3_ACK
#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT                                                            0x10
#define MMVM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK                                                              0x00010000L
//MMVM_INVALIDATE_ENG4_ACK
#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT                                                            0x10
#define MMVM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK                                                              0x00010000L
//MMVM_INVALIDATE_ENG5_ACK
#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT                                                            0x10
#define MMVM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK                                                              0x00010000L
//MMVM_INVALIDATE_ENG6_ACK
#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT                                                            0x10
#define MMVM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK                                                              0x00010000L
//MMVM_INVALIDATE_ENG7_ACK
#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT                                                            0x10
#define MMVM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK                                                              0x00010000L
//MMVM_INVALIDATE_ENG8_ACK
#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT                                                            0x10
#define MMVM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK                                                              0x00010000L
//MMVM_INVALIDATE_ENG9_ACK
#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                              0x0
#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT                                                            0x10
#define MMVM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK                                                0x0000FFFFL
#define MMVM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK                                                              0x00010000L
//MMVM_INVALIDATE_ENG10_ACK
#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
#define MMVM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK                                                             0x00010000L
//MMVM_INVALIDATE_ENG11_ACK
#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
#define MMVM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK                                                             0x00010000L
//MMVM_INVALIDATE_ENG12_ACK
#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
#define MMVM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK                                                             0x00010000L
//MMVM_INVALIDATE_ENG13_ACK
#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
#define MMVM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK                                                             0x00010000L
//MMVM_INVALIDATE_ENG14_ACK
#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
#define MMVM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK                                                             0x00010000L
//MMVM_INVALIDATE_ENG15_ACK
#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
#define MMVM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK                                                             0x00010000L
//MMVM_INVALIDATE_ENG16_ACK
#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
#define MMVM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK                                                             0x00010000L
//MMVM_INVALIDATE_ENG17_ACK
#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT                                             0x0
#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT                                                           0x10
#define MMVM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK                                               0x0000FFFFL
#define MMVM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK                                                             0x00010000L
//MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define MMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define MMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define MMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define MMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define MMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define MMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define MMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define MMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define MMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT                                                    0x0
#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                                0x1
#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK                                                      0x00000001L
#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                  0xFFFFFFFEL
//MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                 0x0
#define MMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                   0x0000001FL
//MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
//MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
#define MMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
//MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
//MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
#define MMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
//MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
//MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
#define MMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
//MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
//MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
#define MMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
//MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
//MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
#define MMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
//MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
//MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
#define MMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
//MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
//MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
#define MMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
//MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32
#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT                                                   0x0
#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT                               0x1
#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK                                                     0x00000001L
#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK                                 0xFFFFFFFEL
//MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32
#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT                                0x0
#define MMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK                                  0x0000001FL
//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define MMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define MMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define MMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define MMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define MMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define MMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define MMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define MMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define MMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                             0x0
#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                             0x0
#define MMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
#define MMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
#define MMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
#define MMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
#define MMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
#define MMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32
#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT                            0x0
#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32
#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT                            0x0
#define MMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32
#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32
#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define MMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32
#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32
#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define MMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32
#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32
#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define MMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32
#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32
#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define MMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32
#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32
#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define MMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32
#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32
#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define MMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32
#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32
#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define MMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32
#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32
#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define MMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32
#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32
#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define MMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32
#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                             0x0
#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                               0xFFFFFFFFL
//MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32
#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                              0x0
#define MMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                0x0000000FL
//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32
#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32
#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
#define MMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32
#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32
#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
#define MMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32
#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32
#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
#define MMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32
#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32
#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
#define MMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32
#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32
#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
#define MMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32
#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                            0x0
#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                              0xFFFFFFFFL
//MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32
#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                             0x0
#define MMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                               0x0000000FL
//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32
#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32
#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define MMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32
#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32
#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define MMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32
#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32
#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define MMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32
#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32
#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define MMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32
#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32
#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define MMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32
#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32
#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define MMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32
#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32
#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define MMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32
#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32
#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define MMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32
#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32
#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define MMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32
#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                               0x0
#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                 0xFFFFFFFFL
//MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32
#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                                0x0
#define MMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                  0x0000000FL
//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32
#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32
#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define MMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32
#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32
#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define MMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32
#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32
#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define MMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32
#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32
#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define MMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32
#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32
#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define MMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32
#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT                              0x0
#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK                                0xFFFFFFFFL
//MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32
#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT                               0x0
#define MMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK                                 0x0000000FL
//MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT                       0x0
#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                         0x5
#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                         0xa
#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                         0x0000001FL
#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                           0x000003E0L
#define MMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                           0x0000FC00L
//MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define MMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define MMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define MMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define MMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define MMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define MMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define MMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define MMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define MMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT              0x0
#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT                0x5
#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                                0xa
#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK                0x0000001FL
#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                  0x000003E0L
#define MMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                  0x0000FC00L
//MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
#define MMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
//MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
#define MMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
//MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
#define MMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
//MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
#define MMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
//MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
#define MMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L
//MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES
#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE__SHIFT             0x0
#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT               0x5
#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT__SHIFT                               0xa
#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_SMALLK_FRAGMENT_SIZE_MASK               0x0000001FL
#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK                 0x000003E0L
#define MMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES__BANK_SELECT_MASK                                 0x0000FC00L


// addressBlock: mmhub_mmutcl2_mmvml2pldec
//MMMC_VM_L2_PERFCOUNTER0_CFG
#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                          0x0
#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                      0x8
#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                         0x18
#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                            0x1c
#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                             0x1d
#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                            0x000000FFL
#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
#define MMMC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                           0x0F000000L
#define MMMC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                              0x10000000L
#define MMMC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                               0x20000000L
//MMMC_VM_L2_PERFCOUNTER1_CFG
#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                          0x0
#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                      0x8
#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                         0x18
#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                            0x1c
#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                             0x1d
#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                            0x000000FFL
#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
#define MMMC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                           0x0F000000L
#define MMMC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                              0x10000000L
#define MMMC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                               0x20000000L
//MMMC_VM_L2_PERFCOUNTER2_CFG
#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                          0x0
#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                      0x8
#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                         0x18
#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                            0x1c
#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                             0x1d
#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                            0x000000FFL
#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
#define MMMC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                           0x0F000000L
#define MMMC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK                                                              0x10000000L
#define MMMC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK                                                               0x20000000L
//MMMC_VM_L2_PERFCOUNTER3_CFG
#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                          0x0
#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                      0x8
#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                         0x18
#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                            0x1c
#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                             0x1d
#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                            0x000000FFL
#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
#define MMMC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                           0x0F000000L
#define MMMC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK                                                              0x10000000L
#define MMMC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK                                                               0x20000000L
//MMMC_VM_L2_PERFCOUNTER4_CFG
#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT                                                          0x0
#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT                                                      0x8
#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT                                                         0x18
#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT                                                            0x1c
#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT                                                             0x1d
#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK                                                            0x000000FFL
#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
#define MMMC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK                                                           0x0F000000L
#define MMMC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK                                                              0x10000000L
#define MMMC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK                                                               0x20000000L
//MMMC_VM_L2_PERFCOUNTER5_CFG
#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT                                                          0x0
#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT                                                      0x8
#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT                                                         0x18
#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT                                                            0x1c
#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT                                                             0x1d
#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK                                                            0x000000FFL
#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
#define MMMC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK                                                           0x0F000000L
#define MMMC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK                                                              0x10000000L
#define MMMC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK                                                               0x20000000L
//MMMC_VM_L2_PERFCOUNTER6_CFG
#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT                                                          0x0
#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT                                                      0x8
#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT                                                         0x18
#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT                                                            0x1c
#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT                                                             0x1d
#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK                                                            0x000000FFL
#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
#define MMMC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK                                                           0x0F000000L
#define MMMC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK                                                              0x10000000L
#define MMMC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK                                                               0x20000000L
//MMMC_VM_L2_PERFCOUNTER7_CFG
#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT                                                          0x0
#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT                                                      0x8
#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT                                                         0x18
#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT                                                            0x1c
#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT                                                             0x1d
#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK                                                            0x000000FFL
#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK                                                        0x0000FF00L
#define MMMC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK                                                           0x0F000000L
#define MMMC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK                                                              0x10000000L
#define MMMC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK                                                               0x20000000L
//MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL
#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                          0x0
#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                0x8
#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                 0x10
#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                   0x18
#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                    0x19
#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                         0x1a
#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                            0x0000000FL
#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                  0x0000FF00L
#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                   0x00FF0000L
#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                     0x01000000L
#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                      0x02000000L
#define MMMC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                           0x04000000L
//MMUTCL2_PERFCOUNTER0_CFG
#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                             0x0
#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                         0x8
#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                            0x18
#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                               0x1c
#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                0x1d
#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                               0x000000FFL
#define MMUTCL2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
#define MMUTCL2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                              0x0F000000L
#define MMUTCL2_PERFCOUNTER0_CFG__ENABLE_MASK                                                                 0x10000000L
#define MMUTCL2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                  0x20000000L
//MMUTCL2_PERFCOUNTER1_CFG
#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                             0x0
#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                         0x8
#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                            0x18
#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                               0x1c
#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                0x1d
#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                               0x000000FFL
#define MMUTCL2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
#define MMUTCL2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                              0x0F000000L
#define MMUTCL2_PERFCOUNTER1_CFG__ENABLE_MASK                                                                 0x10000000L
#define MMUTCL2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                  0x20000000L
//MMUTCL2_PERFCOUNTER2_CFG
#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                             0x0
#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                         0x8
#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                            0x18
#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                               0x1c
#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                0x1d
#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                               0x000000FFL
#define MMUTCL2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
#define MMUTCL2_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                              0x0F000000L
#define MMUTCL2_PERFCOUNTER2_CFG__ENABLE_MASK                                                                 0x10000000L
#define MMUTCL2_PERFCOUNTER2_CFG__CLEAR_MASK                                                                  0x20000000L
//MMUTCL2_PERFCOUNTER3_CFG
#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                             0x0
#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                         0x8
#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                            0x18
#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                               0x1c
#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                                0x1d
#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                               0x000000FFL
#define MMUTCL2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
#define MMUTCL2_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                              0x0F000000L
#define MMUTCL2_PERFCOUNTER3_CFG__ENABLE_MASK                                                                 0x10000000L
#define MMUTCL2_PERFCOUNTER3_CFG__CLEAR_MASK                                                                  0x20000000L
//MMUTCL2_PERFCOUNTER_RSLT_CNTL
#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                             0x0
#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                   0x8
#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                    0x10
#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                      0x18
#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                       0x19
#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                            0x1a
#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                               0x0000000FL
#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                     0x0000FF00L
#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                      0x00FF0000L
#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                        0x01000000L
#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                         0x02000000L
#define MMUTCL2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                              0x04000000L


// addressBlock: mmhub_mmutcl2_mmvml2prdec
//MMMC_VM_L2_PERFCOUNTER_LO
#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                          0x0
#define MMMC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                            0xFFFFFFFFL
//MMMC_VM_L2_PERFCOUNTER_HI
#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                          0x0
#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                       0x10
#define MMMC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                            0x0000FFFFL
#define MMMC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                         0xFFFF0000L
//MMUTCL2_PERFCOUNTER_LO
#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                             0x0
#define MMUTCL2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                               0xFFFFFFFFL
//MMUTCL2_PERFCOUNTER_HI
#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                             0x0
#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                          0x10
#define MMUTCL2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                               0x0000FFFFL
#define MMUTCL2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                            0xFFFF0000L


// addressBlock: mmhub_mmutcl2_mmvmsharedhvdec
//MMVM_PCIE_ATS_CNTL
#define MMVM_PCIE_ATS_CNTL__STU__SHIFT                                                                        0x10
#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                                 0x1f
#define MMVM_PCIE_ATS_CNTL__STU_MASK                                                                          0x001F0000L
#define MMVM_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                                   0x80000000L


// addressBlock: mmhub_mmutcl2_mmvmsharedpfdec
//MMMC_VM_NB_MMIOBASE
#define MMMC_VM_NB_MMIOBASE__MMIOBASE__SHIFT                                                                  0x0
#define MMMC_VM_NB_MMIOBASE__MMIOBASE_MASK                                                                    0xFFFFFFFFL
//MMMC_VM_NB_MMIOLIMIT
#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT                                                                0x0
#define MMMC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK                                                                  0xFFFFFFFFL
//MMMC_VM_NB_PCI_CTRL
#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT                                                                0x17
#define MMMC_VM_NB_PCI_CTRL__MMIOENABLE_MASK                                                                  0x00800000L
//MMMC_VM_NB_PCI_ARB
#define MMMC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT                                                                   0x3
#define MMMC_VM_NB_PCI_ARB__VGA_HOLE_MASK                                                                     0x00000008L
//MMMC_VM_NB_TOP_OF_DRAM_SLOT1
#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT                                                      0x17
#define MMMC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK                                                        0xFF800000L
//MMMC_VM_NB_LOWER_TOP_OF_DRAM2
#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT                                                          0x0
#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT                                                      0x17
#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK                                                            0x00000001L
#define MMMC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK                                                        0xFF800000L
//MMMC_VM_NB_UPPER_TOP_OF_DRAM2
#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT                                                      0x0
#define MMMC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK                                                        0x00000FFFL
//MMMC_VM_FB_OFFSET
#define MMMC_VM_FB_OFFSET__FB_OFFSET__SHIFT                                                                   0x0
#define MMMC_VM_FB_OFFSET__FB_OFFSET_MASK                                                                     0x00FFFFFFL
//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB
#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT                             0x0
#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK                               0xFFFFFFFFL
//MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB
#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT                             0x0
#define MMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK                               0x0000000FL
//MMMC_VM_STEERING
#define MMMC_VM_STEERING__DEFAULT_STEERING__SHIFT                                                             0x0
#define MMMC_VM_STEERING__DEFAULT_STEERING_MASK                                                               0x00000003L
//MMMC_SHARED_VIRT_RESET_REQ
#define MMMC_SHARED_VIRT_RESET_REQ__VF__SHIFT                                                                 0x0
#define MMMC_SHARED_VIRT_RESET_REQ__PF__SHIFT                                                                 0x1f
#define MMMC_SHARED_VIRT_RESET_REQ__VF_MASK                                                                   0x0000FFFFL
#define MMMC_SHARED_VIRT_RESET_REQ__PF_MASK                                                                   0x80000000L
//MMMC_MEM_POWER_LS
#define MMMC_MEM_POWER_LS__LS_SETUP__SHIFT                                                                    0x0
#define MMMC_MEM_POWER_LS__LS_HOLD__SHIFT                                                                     0x6
#define MMMC_MEM_POWER_LS__LS_SETUP_MASK                                                                      0x0000003FL
#define MMMC_MEM_POWER_LS__LS_HOLD_MASK                                                                       0x00000FC0L
//MMMC_VM_CACHEABLE_DRAM_ADDRESS_START
#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT                                                  0x0
#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK                                                    0x000FFFFFL
//MMMC_VM_CACHEABLE_DRAM_ADDRESS_END
#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT                                                    0x0
#define MMMC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK                                                      0x000FFFFFL
//MMMC_VM_LOCAL_SYSMEM_ADDRESS_START
#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS__SHIFT                                                    0x0
#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_START__ADDRESS_MASK                                                      0x000FFFFFL
//MMMC_VM_LOCAL_SYSMEM_ADDRESS_END
#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS__SHIFT                                                      0x0
#define MMMC_VM_LOCAL_SYSMEM_ADDRESS_END__ADDRESS_MASK                                                        0x000FFFFFL
//MMMC_VM_APT_CNTL
#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT                                                               0x0
#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT                                                             0x1
#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE__SHIFT                                                          0x2
#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT                                                               0x4
#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M__SHIFT                                                             0x5
#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL__SHIFT                                                   0x6
#define MMMC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK                                                                 0x00000001L
#define MMMC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK                                                               0x00000002L
#define MMMC_VM_APT_CNTL__FRAG_APT_INTXN_MODE_MASK                                                            0x0000000CL
#define MMMC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK                                                                 0x00000010L
#define MMMC_VM_APT_CNTL__CAP_FRAG_SIZE_2M_MASK                                                               0x00000020L
#define MMMC_VM_APT_CNTL__LOCAL_SYSMEM_APERTURE_CNTL_MASK                                                     0x000000C0L
//MMMC_VM_LOCAL_FB_ADDRESS_START
#define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS__SHIFT                                                        0x0
#define MMMC_VM_LOCAL_FB_ADDRESS_START__ADDRESS_MASK                                                          0x000FFFFFL
//MMMC_VM_LOCAL_FB_ADDRESS_END
#define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS__SHIFT                                                          0x0
#define MMMC_VM_LOCAL_FB_ADDRESS_END__ADDRESS_MASK                                                            0x000FFFFFL
//MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL
#define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK__SHIFT                                                       0x0
#define MMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL__LOCK_MASK                                                         0x00000001L
//MMUTCL2_CGTT_CLK_CTRL
#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT                                                                0x0
#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT                                                          0x5
#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS__SHIFT                                                    0xd
#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE__SHIFT                                                              0x1e
#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE__SHIFT                                                           0x1f
#define MMUTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK                                                                  0x0000001FL
#define MMUTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK                                                            0x00001FE0L
#define MMUTCL2_CGTT_CLK_CTRL__LS_ASSERT_HYSTERESIS_MASK                                                      0x1FFFE000L
#define MMUTCL2_CGTT_CLK_CTRL__LS_DISABLE_MASK                                                                0x40000000L
#define MMUTCL2_CGTT_CLK_CTRL__BUSY_OVERRIDE_MASK                                                             0x80000000L
//MMMC_SHARED_ACTIVE_FCN_ID
#define MMMC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT                                                                0x0
#define MMMC_SHARED_ACTIVE_FCN_ID__VF__SHIFT                                                                  0x1e
#define MMMC_SHARED_ACTIVE_FCN_ID__VFID_MASK                                                                  0x0000000FL
#define MMMC_SHARED_ACTIVE_FCN_ID__VF_MASK                                                                    0x40000000L
//MMUTCL2_CGTT_BUSY_CTRL
#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT                                                             0x0
#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT                                                            0x5
#define MMUTCL2_CGTT_BUSY_CTRL__READ_DELAY_MASK                                                               0x0000001FL
#define MMUTCL2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK                                                              0x00000020L
//MMUTCL2_HARVEST_BYPASS_GROUPS
#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS__SHIFT                                                   0x0
#define MMUTCL2_HARVEST_BYPASS_GROUPS__BYPASS_GROUPS_MASK                                                     0xFFFFFFFFL
//MMUTCL2_GROUP_RET_FAULT_STATUS
#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS__SHIFT                                                   0x0
#define MMUTCL2_GROUP_RET_FAULT_STATUS__FAULT_GROUPS_MASK                                                     0xFFFFFFFFL


// addressBlock: mmhub_mmutcl2_mmvmsharedvcdec
//MMMC_VM_FB_LOCATION_BASE
#define MMMC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT                                                              0x0
#define MMMC_VM_FB_LOCATION_BASE__FB_BASE_MASK                                                                0x00FFFFFFL
//MMMC_VM_FB_LOCATION_TOP
#define MMMC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT                                                                0x0
#define MMMC_VM_FB_LOCATION_TOP__FB_TOP_MASK                                                                  0x00FFFFFFL
//MMMC_VM_AGP_TOP
#define MMMC_VM_AGP_TOP__AGP_TOP__SHIFT                                                                       0x0
#define MMMC_VM_AGP_TOP__AGP_TOP_MASK                                                                         0x00FFFFFFL
//MMMC_VM_AGP_BOT
#define MMMC_VM_AGP_BOT__AGP_BOT__SHIFT                                                                       0x0
#define MMMC_VM_AGP_BOT__AGP_BOT_MASK                                                                         0x00FFFFFFL
//MMMC_VM_AGP_BASE
#define MMMC_VM_AGP_BASE__AGP_BASE__SHIFT                                                                     0x0
#define MMMC_VM_AGP_BASE__AGP_BASE_MASK                                                                       0x00FFFFFFL
//MMMC_VM_SYSTEM_APERTURE_LOW_ADDR
#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT                                                 0x0
#define MMMC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK                                                   0x3FFFFFFFL
//MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR
#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT                                                0x0
#define MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK                                                  0x3FFFFFFFL
//MMMC_VM_MX_L1_TLB_CNTL
#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT                                                          0x0
#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT                                                     0x3
#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT                                        0x5
#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT                                           0x6
#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT                                                               0x7
#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT                                                                  0xb
#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK                                                            0x00000001L
#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK                                                       0x00000018L
#define MMMC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK                                          0x00000020L
#define MMMC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK                                             0x00000040L
#define MMMC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK                                                                 0x00000780L
#define MMMC_VM_MX_L1_TLB_CNTL__MTYPE_MASK                                                                    0x00003800L


// addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec
//MM_ATC_L2_PERFCOUNTER_LO
#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                           0x0
#define MM_ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK                                                             0xFFFFFFFFL
//MM_ATC_L2_PERFCOUNTER_HI
#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                           0x0
#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                        0x10
#define MM_ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK                                                             0x0000FFFFL
#define MM_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                          0xFFFF0000L


// addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec
//MM_ATC_L2_PERFCOUNTER0_CFG
#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                           0x0
#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                       0x8
#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                          0x18
#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                             0x1c
#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                              0x1d
#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                             0x000000FFL
#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                         0x0000FF00L
#define MM_ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                            0x0F000000L
#define MM_ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK                                                               0x10000000L
#define MM_ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK                                                                0x20000000L
//MM_ATC_L2_PERFCOUNTER1_CFG
#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                           0x0
#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                       0x8
#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                          0x18
#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                             0x1c
#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                              0x1d
#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                             0x000000FFL
#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                         0x0000FF00L
#define MM_ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                            0x0F000000L
#define MM_ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK                                                               0x10000000L
#define MM_ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK                                                                0x20000000L
//MM_ATC_L2_PERFCOUNTER_RSLT_CNTL
#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                           0x0
#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                 0x8
#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                  0x10
#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                    0x18
#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                     0x19
#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                          0x1a
#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                             0x0000000FL
#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                   0x0000FF00L
#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                    0x00FF0000L
#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                      0x01000000L
#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                       0x02000000L
#define MM_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                            0x04000000L


// addressBlock: mmhub_mmutcl2_mmvml2pspdec
//MMUTCL2_TRANSLATION_BYPASS_BY_VMID
#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS__SHIFT                                         0x0
#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS__SHIFT                                             0x10
#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__TRANS_BYPASS_VMIDS_MASK                                           0x0000FFFFL
#define MMUTCL2_TRANSLATION_BYPASS_BY_VMID__GPA_MODE_VMIDS_MASK                                               0xFFFF0000L
//MMVM_IOMMU_CONTROL_REGISTER
#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT                                                           0x0
#define MMVM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK                                                             0x00000001L
//MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER
#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT                                0xd
#define MMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK                                  0x00002000L
//MMUTC_TRANSLATION_FAULT_CNTL0
#define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB__SHIFT                               0x0
#define MMUTC_TRANSLATION_FAULT_CNTL0__DEFAULT_PHYSICAL_PAGE_ADDRESS_LSB_MASK                                 0xFFFFFFFFL
//MMUTC_TRANSLATION_FAULT_CNTL1
#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB__SHIFT                               0x0
#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO__SHIFT                                                      0x4
#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA__SHIFT                                                     0x5
#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP__SHIFT                                                   0x6
#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_PHYSICAL_PAGE_ADDRESS_MSB_MASK                                 0x0000000FL
#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_IO_MASK                                                        0x00000010L
#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SPA_MASK                                                       0x00000020L
#define MMUTC_TRANSLATION_FAULT_CNTL1__DEFAULT_SNOOP_MASK                                                     0x00000040L


// addressBlock: mmhub_mmutcl2_mml2tlbpspdec
//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE__SHIFT                                               0x0
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL__ENABLE_MASK                                                 0x00000001L


// addressBlock: mmhub_mmutcl2_mmatcl2pspdec
//MM_ATC_L2_IOV_MODE_CNTL
#define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN__SHIFT                                                         0x0
#define MM_ATC_L2_IOV_MODE_CNTL__PSEUDO_IOV_EN_MASK                                                           0x00000001L


// addressBlock: mmhub_mmutcl2_mml2tlbpfdec
//MML2TLB_TLB0_STATUS
#define MML2TLB_TLB0_STATUS__BUSY__SHIFT                                                                      0x0
#define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT                                                       0x1
#define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS__SHIFT                                                     0x2
#define MML2TLB_TLB0_STATUS__BUSY_MASK                                                                        0x00000001L
#define MML2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK                                                         0x00000002L
#define MML2TLB_TLB0_STATUS__FOUND_APERTURE_FAULTS_MASK                                                       0x00000004L
//MML2TLB_TMZ_CNTL
#define MML2TLB_TMZ_CNTL__TMZ_MODULATION__SHIFT                                                               0x0
#define MML2TLB_TMZ_CNTL__TMZ_MODULATION_MASK                                                                 0x00000001L
//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT                                           0x0
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK                                             0xFFFFFFFFL
//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT                                           0x0
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT                                           0x4
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT                                           0x8
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT                                             0xc
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT                                            0xd
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT                                        0xf
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT                                        0x10
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT                                        0x11
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT                                      0x12
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT                                            0x1e
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK                                             0x0000000FL
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK                                             0x000000F0L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK                                             0x00000F00L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK                                               0x00001000L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK                                              0x00006000L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK                                          0x00008000L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK                                          0x00010000L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK                                          0x00020000L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK                                        0x07FC0000L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK                                              0x40000000L
//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT                                          0x0
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK                                            0xFFFFFFFFL
//MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT                                          0x0
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT                                         0x4
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT                                 0x7
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT                                         0xd
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT                                           0xe
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT                                            0xf
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT                                       0x10
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT                                        0x11
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT                                         0x12
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT                                        0x15
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT                                          0x16
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC__SHIFT                                   0x18
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT                                           0x1f
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK                                            0x0000000FL
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK                                           0x00000070L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK                                   0x00001F80L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK                                           0x00002000L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK                                             0x00004000L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK                                              0x00008000L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK                                         0x00010000L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK                                          0x00020000L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK                                           0x001C0000L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK                                          0x00200000L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK                                            0x00C00000L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__LLC_NOALLOC_MASK                                     0x01000000L
#define MMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK                                             0x80000000L
//MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ
#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS__SHIFT                                               0x0
#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE__SHIFT                                                 0xa
#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__CREDITS_MASK                                                 0x000003FFL
#define MMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ__WRITE_MASK                                                   0x00000400L


// addressBlock: mmhub_mmutcl2_mml2tlbpldec
//MML2TLB_PERFCOUNTER0_CFG
#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                             0x0
#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                         0x8
#define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                            0x18
#define MML2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                               0x1c
#define MML2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                                0x1d
#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                               0x000000FFL
#define MML2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
#define MML2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                              0x0F000000L
#define MML2TLB_PERFCOUNTER0_CFG__ENABLE_MASK                                                                 0x10000000L
#define MML2TLB_PERFCOUNTER0_CFG__CLEAR_MASK                                                                  0x20000000L
//MML2TLB_PERFCOUNTER1_CFG
#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                             0x0
#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                         0x8
#define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                            0x18
#define MML2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                               0x1c
#define MML2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                                0x1d
#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                               0x000000FFL
#define MML2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
#define MML2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                              0x0F000000L
#define MML2TLB_PERFCOUNTER1_CFG__ENABLE_MASK                                                                 0x10000000L
#define MML2TLB_PERFCOUNTER1_CFG__CLEAR_MASK                                                                  0x20000000L
//MML2TLB_PERFCOUNTER2_CFG
#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                             0x0
#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                         0x8
#define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                            0x18
#define MML2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                               0x1c
#define MML2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                                0x1d
#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                               0x000000FFL
#define MML2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
#define MML2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                              0x0F000000L
#define MML2TLB_PERFCOUNTER2_CFG__ENABLE_MASK                                                                 0x10000000L
#define MML2TLB_PERFCOUNTER2_CFG__CLEAR_MASK                                                                  0x20000000L
//MML2TLB_PERFCOUNTER3_CFG
#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                             0x0
#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                         0x8
#define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                            0x18
#define MML2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                               0x1c
#define MML2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                                0x1d
#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                               0x000000FFL
#define MML2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                           0x0000FF00L
#define MML2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                              0x0F000000L
#define MML2TLB_PERFCOUNTER3_CFG__ENABLE_MASK                                                                 0x10000000L
#define MML2TLB_PERFCOUNTER3_CFG__CLEAR_MASK                                                                  0x20000000L
//MML2TLB_PERFCOUNTER_RSLT_CNTL
#define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                             0x0
#define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                                   0x8
#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                                    0x10
#define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                      0x18
#define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                       0x19
#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                            0x1a
#define MML2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                               0x0000000FL
#define MML2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                     0x0000FF00L
#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                      0x00FF0000L
#define MML2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                        0x01000000L
#define MML2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                         0x02000000L
#define MML2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                              0x04000000L


// addressBlock: mmhub_mmutcl2_mml2tlbprdec
//MML2TLB_PERFCOUNTER_LO
#define MML2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                             0x0
#define MML2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK                                                               0xFFFFFFFFL
//MML2TLB_PERFCOUNTER_HI
#define MML2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                             0x0
#define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                          0x10
#define MML2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK                                                               0x0000FFFFL
#define MML2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                            0xFFFF0000L

#endif