| /* SPDX-License-Identifier: GPL-2.0-only */ |
| /* |
| * Copyright (C) 2016 - ARM Ltd |
| * |
| * stage2 page table helpers |
| */ |
| |
| #ifndef __ARM64_S2_PGTABLE_H_ |
| #define __ARM64_S2_PGTABLE_H_ |
| |
| #include <linux/pgtable.h> |
| |
| /* |
| * PGDIR_SHIFT determines the size a top-level page table entry can map |
| * and depends on the number of levels in the page table. Compute the |
| * PGDIR_SHIFT for a given number of levels. |
| */ |
| #define pt_levels_pgdir_shift(lvls) ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - (lvls)) |
| |
| /* |
| * The hardware supports concatenation of up to 16 tables at stage2 entry |
| * level and we use the feature whenever possible, which means we resolve 4 |
| * additional bits of address at the entry level. |
| * |
| * This implies, the total number of page table levels required for |
| * IPA_SHIFT at stage2 expected by the hardware can be calculated using |
| * the same logic used for the (non-collapsable) stage1 page tables but for |
| * (IPA_SHIFT - 4). |
| */ |
| #define stage2_pgtable_levels(ipa) ARM64_HW_PGTABLE_LEVELS((ipa) - 4) |
| #define kvm_stage2_levels(kvm) VTCR_EL2_LVLS(kvm->arch.vtcr) |
| |
| /* stage2_pgdir_shift() is the size mapped by top-level stage2 entry for the VM */ |
| #define stage2_pgdir_shift(kvm) pt_levels_pgdir_shift(kvm_stage2_levels(kvm)) |
| #define stage2_pgdir_size(kvm) (1ULL << stage2_pgdir_shift(kvm)) |
| #define stage2_pgdir_mask(kvm) ~(stage2_pgdir_size(kvm) - 1) |
| |
| /* |
| * kvm_mmmu_cache_min_pages() is the number of pages required to install |
| * a stage-2 translation. We pre-allocate the entry level page table at |
| * the VM creation. |
| */ |
| #define kvm_mmu_cache_min_pages(kvm) (kvm_stage2_levels(kvm) - 1) |
| |
| static inline phys_addr_t |
| stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) |
| { |
| phys_addr_t boundary = (addr + stage2_pgdir_size(kvm)) & stage2_pgdir_mask(kvm); |
| |
| return (boundary - 1 < end - 1) ? boundary : end; |
| } |
| |
| #endif /* __ARM64_S2_PGTABLE_H_ */ |
