tree e3df0513cafc45196b9dcf12bc03a5918ce33cad
parent 68dec269ee29c3abfd09596fbee7e40d875a6ab3
author Quentin Schulz <quentin.schulz@bootlin.com> 1538993684 +0200
committer Paul Burton <paul.burton@mips.com> 1539106647 -0700
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iIsEABYIADMWIQRgLjeFAZEXQzy86/s+p5+stXUA3QUCW7znlRUccGF1bC5idXJ0
 b25AbWlwcy5jb20ACgkQPqefrLV1AN1M0wEA0i6xFpE2lP1xGdMLkMjEpSBf84tv
 tV2IV6iLiqPhgqsBAMIlnpq0lbC/nIT6y1UtwwzNNJ5B4G5oeMj5J8bIp6EG
 =Mmt8
 -----END PGP SIGNATURE-----

MIPS: mscc: add DT for Ocelot PCB120

The Ocelot PCB120 evaluation board is different from the PCB123 in that
it has 4 external VSC8584 (or VSC8574) PHYs.

It uses the SoC's second MDIO bus for external PHYs which have a
reversed address on the bus (i.e. PHY4 is on address 3, PHY5 is on
address 2, PHY6 on 1 and PHY7 on 0).

Here is how the PHYs are connected to the switch ports:
port 0: phy0 (internal)
port 1: phy1 (internal)
port 2: phy2 (internal)
port 3: phy3 (internal)
port 4: phy7
port 5: phy4
port 6: phy6
port 9: phy5

Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/20869/
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: robh+dt@kernel.org
Cc: mark.rutland@arm.com
Cc: davem@davemloft.net
Cc: andrew@lunn.ch
Cc: f.fainelli@gmail.com
Cc: allan.nielsen@microchip.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: netdev@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com
Cc: antoine.tenart@bootlin.com