| commit | b8ab8e041cc0356323c1e4aee8047ea479650340 | [log] [tgz] |
|---|---|---|
| author | Shawn Lin <shawn.lin@rock-chips.com> | Wed Dec 07 15:05:58 2016 -0600 |
| committer | Bjorn Helgaas <bhelgaas@google.com> | Wed Dec 07 15:05:58 2016 -0600 |
| tree | ea3ee0e51fb9849440427e86196eb42d58738e4c | |
| parent | 4816c4c7b82b55bb46cb9b85ef8e6780fc618592 [diff] |
PCI: rockchip: Mark RC as common clock architecture The default value of common clock configuration is zero indicating Rockchip's RC is using asynchronous clock architecture but actually we are using common clock. This will confuse some EP drivers if they need some different settings referring to this value. Set the Common Clock Configuration bit in the Link Control Register. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>