tree 8ae1d6a30cc5864c7f631baff88fc94275184f1a
parent f80e21489590c00f46226d5802d900e6f66e5633
parent f196ae282070d798c9144771db65577910d58566
author Thomas Gleixner <tglx@linutronix.de> 1629994850 +0200
committer Thomas Gleixner <tglx@linutronix.de> 1629994850 +0200
mergetag object f196ae282070d798c9144771db65577910d58566
 type commit
 tag timers-v5.15
 tagger Daniel Lezcano <daniel.lezcano@linaro.org> 1629785816 +0200
 
 - Prioritize the ARM architected timer on Exynos platform when the
   architecture is ARM64 (Will Deacon)
 
 - Mark the Exynos timer as a per CPU timer (Will Deacon)
 
 - DT conversion to yaml for the rockchip platform (Ezequiel Garcia)
 
 - Fix IRQ setup if there are two channels on the sh_cmt timer (Phong
   Hoang)
 
 - Use bitfield helper macros in the Ingenic timer (Zhou Yanjie)
 
 - Clear any pending interrupt to prevent an abort of the suspend on
   the Mediatek platform (Fengquan Chen)
 
 - Add DT bindings for new Ingenic SoCs (Zhou Yanjie)
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Merge tag 'timers-v5.15' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core

Pull timer driver updates from Daniel Lezcano:

 - Prioritize the ARM architected timer on Exynos platform when the
   architecture is ARM64 (Will Deacon)

 - Mark the Exynos timer as a per CPU timer (Will Deacon)

 - DT conversion to yaml for the rockchip platform (Ezequiel Garcia)

 - Fix IRQ setup if there are two channels on the sh_cmt timer (Phong
   Hoang)

 - Use bitfield helper macros in the Ingenic timer (Zhou Yanjie)

 - Clear any pending interrupt to prevent an abort of the suspend on
   the Mediatek platform (Fengquan Chen)

 - Add DT bindings for new Ingenic SoCs (Zhou Yanjie)

Link: https://lore.kernel.org/r/c14ad27a-b1c6-6043-0f5e-71dd984bb4ba@linaro.org