commit 130fe357ee895421a4aefef7b1285bf52f295afe
author Markos Chandras <markos.chandras@imgtec.com> Thu Aug 13 09:56:30 2015 +0200
committer Ralf Baechle <ralf@linux-mips.org> Thu Sep 03 12:08:13 2015 +0200
tree d21c7a7f04c28fcbc62d925b9c2ef86e550f0d0d
parent 67613f02788d73541c7c9b1c851061b8c223057b

MIPS: math-emu: Add support for the MIPS R6 SELNEZ FPU instruction

MIPS R6 introduced the following instruction:
SELNEZ.fmt: FPR[fd]  FPR[ft].bit0 ? FPR[fs] : 0

Add support for emulating the single and double precision
formats of the said instruction.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10955/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

arch/mips/math-emu/cp1emu.c

diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 02ba536..8978d52 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -1754,6 +1754,17 @@
 				SPFROMREG(rv.s, MIPSInst_FS(ir));
 			break;
 
+		case fselnez_op:
+			if (!cpu_has_mips_r6)
+				return SIGILL;
+
+			SPFROMREG(rv.s, MIPSInst_FT(ir));
+			if (rv.w & 0x1)
+				SPFROMREG(rv.s, MIPSInst_FS(ir));
+			else
+				rv.w = 0;
+			break;
+
 		case fabs_op:
 			handler.u = ieee754sp_abs;
 			goto scopuop;
@@ -1963,6 +1974,17 @@
 				DPFROMREG(rv.d, MIPSInst_FS(ir));
 			break;
 
+		case fselnez_op:
+			if (!cpu_has_mips_r6)
+				return SIGILL;
+
+			DPFROMREG(rv.d, MIPSInst_FT(ir));
+			if (rv.l & 0x1)
+				DPFROMREG(rv.d, MIPSInst_FS(ir));
+			else
+				rv.l = 0;
+			break;
+
 		case fabs_op:
 			handler.u = ieee754dp_abs;
 			goto dcopuop;