| commit | 137d264c6f63f5b57200b8becb00d7cc58163c05 | [log] [tgz] |
|---|---|---|
| author | Mustafa Ismail <mustafa.ismail@intel.com> | Tue Jul 05 18:08:09 2022 -0500 |
| committer | Leon Romanovsky <leonro@nvidia.com> | Mon Jul 18 10:39:28 2022 +0300 |
| tree | 1d6a2413d77d7f84d1f2b381ae5d04daa2916be8 | |
| parent | 2157f5caaed59128d70a1dd72f5ec809cad54407 [diff] |
RDMA/irdma: Add 2 level PBLE support for FMR Level 2 Physical Buffer List Entry (PBLE) is currently not supported for Fast MRs which limits memory registrations to 256K pages. Adapt irdma_set_page and irdma_alloc_mr to allow for 2 level PBLEs. Link: https://lore.kernel.org/r/20220705230815.265-2-shiraz.saleem@intel.com Signed-off-by: Mustafa Ismail <mustafa.ismail@intel.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Leon Romanovsky <leon@kernel.org>