tree ebc8e171a82bb4743fbcc27de067fcf79a261046
parent 11ad470c5486ab848f04418c56d58f078ad53a9a
author Chen-Yu Tsai <wens@csie.org> 1495177568 +0800
committer Maxime Ripard <maxime.ripard@free-electrons.com> 1496842335 +0200

clk: sunxi-ng: Support multiple variable pre-dividers

On the A83T, the AHB1 clock has a shared pre-divider on the two
PLL-PERIPH clock parents. To support such instances of shared
pre-dividers, this patch extends the mux clock type to support
multiple variable pre-dividers.

As the pre-dividers are only used to calculate the rate, but
do not participate in the factorization process, this is fairly
straightforward.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>