| commit | 2110add84bc6e21a1bf55f2c9d1fc14d408ce2e0 | [log] [tgz] |
|---|---|---|
| author | Xingyu Wu <xingyu.wu@starfivetech.com> | Mon Jul 17 10:30:36 2023 +0800 |
| committer | Conor Dooley <conor.dooley@microchip.com> | Wed Jul 19 18:08:00 2023 +0100 |
| tree | b87058bc89d5efd3c1a8c7ef9e47c2d7723f41c3 | |
| parent | c81f7845b2ce7a2ea1beb2ac4621b5d568d2b644 [diff] |
dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Add PLL clock inputs from PLL clock generator. Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>