tree 60bedcdf898484ab156b1e3fd054a6597dceebc8
parent 2110add84bc6e21a1bf55f2c9d1fc14d408ce2e0
author Xingyu Wu <xingyu.wu@starfivetech.com> 1689248334 +0800
committer Conor Dooley <conor.dooley@microchip.com> 1689786480 +0100

dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator

Add bindings for the System-Top-Group clock and reset generator (STGCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>