/*
 * Lite5200 board Device Tree Source
 *
 * Copyright 2006-2007 Secret Lab Technologies Ltd.
 * Grant Likely <grant.likely@secretlab.ca>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

/ {
	model = "fsl,lite5200";
	compatible = "fsl,lite5200";
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,5200@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <20>;
			i-cache-line-size = <20>;
			d-cache-size = <4000>;		// L1, 16K
			i-cache-size = <4000>;		// L1, 16K
			timebase-frequency = <0>;	// from bootloader
			bus-frequency = <0>;		// from bootloader
			clock-frequency = <0>;		// from bootloader
		};
	};

	memory {
		device_type = "memory";
		reg = <00000000 04000000>;	// 64MB
	};

	soc5200@f0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "fsl,mpc5200-immr";
		ranges = <0 f0000000 0000c000>;
		reg = <f0000000 00000100>;
		bus-frequency = <0>;		// from bootloader
		system-frequency = <0>;		// from bootloader

		cdm@200 {
			compatible = "fsl,mpc5200-cdm";
			reg = <200 38>;
		};

		mpc5200_pic: interrupt-controller@500 {
			// 5200 interrupts are encoded into two levels;
			interrupt-controller;
			#interrupt-cells = <3>;
			device_type = "interrupt-controller";
			compatible = "fsl,mpc5200-pic";
			reg = <500 80>;
		};

		timer@600 {	// General Purpose Timer
			compatible = "fsl,mpc5200-gpt";
			cell-index = <0>;
			reg = <600 10>;
			interrupts = <1 9 0>;
			interrupt-parent = <&mpc5200_pic>;
			fsl,has-wdt;
		};

		timer@610 {	// General Purpose Timer
			compatible = "fsl,mpc5200-gpt";
			cell-index = <1>;
			reg = <610 10>;
			interrupts = <1 a 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		timer@620 {	// General Purpose Timer
			compatible = "fsl,mpc5200-gpt";
			cell-index = <2>;
			reg = <620 10>;
			interrupts = <1 b 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		timer@630 {	// General Purpose Timer
			compatible = "fsl,mpc5200-gpt";
			cell-index = <3>;
			reg = <630 10>;
			interrupts = <1 c 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		timer@640 {	// General Purpose Timer
			compatible = "fsl,mpc5200-gpt";
			cell-index = <4>;
			reg = <640 10>;
			interrupts = <1 d 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		timer@650 {	// General Purpose Timer
			compatible = "fsl,mpc5200-gpt";
			cell-index = <5>;
			reg = <650 10>;
			interrupts = <1 e 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		timer@660 {	// General Purpose Timer
			compatible = "fsl,mpc5200-gpt";
			cell-index = <6>;
			reg = <660 10>;
			interrupts = <1 f 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		timer@670 {	// General Purpose Timer
			compatible = "fsl,mpc5200-gpt";
			cell-index = <7>;
			reg = <670 10>;
			interrupts = <1 10 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		rtc@800 {	// Real time clock
			compatible = "fsl,mpc5200-rtc";
			device_type = "rtc";
			reg = <800 100>;
			interrupts = <1 5 0 1 6 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		can@900 {
			compatible = "fsl,mpc5200-mscan";
			cell-index = <0>;
			interrupts = <2 11 0>;
			interrupt-parent = <&mpc5200_pic>;
			reg = <900 80>;
		};

		can@980 {
			compatible = "fsl,mpc5200-mscan";
			cell-index = <1>;
			interrupts = <2 12 0>;
			interrupt-parent = <&mpc5200_pic>;
			reg = <980 80>;
		};

		gpio@b00 {
			compatible = "fsl,mpc5200-gpio";
			reg = <b00 40>;
			interrupts = <1 7 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		gpio@c00 {
			compatible = "fsl,mpc5200-gpio-wkup";
			reg = <c00 40>;
			interrupts = <1 8 0 0 3 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		spi@f00 {
			compatible = "fsl,mpc5200-spi";
			reg = <f00 20>;
			interrupts = <2 d 0 2 e 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		usb@1000 {
			compatible = "fsl,mpc5200-ohci","ohci-be";
			reg = <1000 ff>;
			interrupts = <2 6 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		dma-controller@1200 {
			device_type = "dma-controller";
			compatible = "fsl,mpc5200-bestcomm";
			reg = <1200 80>;
			interrupts = <3 0 0  3 1 0  3 2 0  3 3 0
			              3 4 0  3 5 0  3 6 0  3 7 0
			              3 8 0  3 9 0  3 a 0  3 b 0
			              3 c 0  3 d 0  3 e 0  3 f 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		xlb@1f00 {
			compatible = "fsl,mpc5200-xlb";
			reg = <1f00 100>;
		};

		serial@2000 {		// PSC1
			device_type = "serial";
			compatible = "fsl,mpc5200-psc-uart";
			port-number = <0>;  // Logical port assignment
			cell-index = <0>;
			reg = <2000 100>;
			interrupts = <2 1 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		// PSC2 in ac97 mode example
		//ac97@2200 {		// PSC2
		//	compatible = "fsl,mpc5200-psc-ac97";
		//	cell-index = <1>;
		//	reg = <2200 100>;
		//	interrupts = <2 2 0>;
		//	interrupt-parent = <&mpc5200_pic>;
		//};

		// PSC3 in CODEC mode example
		//i2s@2400 {		// PSC3
		//	compatible = "fsl,mpc5200-psc-i2s";
		//	cell-index = <2>;
		//	reg = <2400 100>;
		//	interrupts = <2 3 0>;
		//	interrupt-parent = <&mpc5200_pic>;
		//};

		// PSC4 in uart mode example
		//serial@2600 {		// PSC4
		//	device_type = "serial";
		//	compatible = "fsl,mpc5200-psc-uart";
		//	cell-index = <3>;
		//	reg = <2600 100>;
		//	interrupts = <2 b 0>;
		//	interrupt-parent = <&mpc5200_pic>;
		//};

		// PSC5 in uart mode example
		//serial@2800 {		// PSC5
		//	device_type = "serial";
		//	compatible = "fsl,mpc5200-psc-uart";
		//	cell-index = <4>;
		//	reg = <2800 100>;
		//	interrupts = <2 c 0>;
		//	interrupt-parent = <&mpc5200_pic>;
		//};

		// PSC6 in spi mode example
		//spi@2c00 {		// PSC6
		//	compatible = "fsl,mpc5200-psc-spi";
		//	cell-index = <5>;
		//	reg = <2c00 100>;
		//	interrupts = <2 4 0>;
		//	interrupt-parent = <&mpc5200_pic>;
		//};

		ethernet@3000 {
			device_type = "network";
			compatible = "fsl,mpc5200-fec";
			reg = <3000 800>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			interrupts = <2 5 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		ata@3a00 {
			device_type = "ata";
			compatible = "fsl,mpc5200-ata";
			reg = <3a00 100>;
			interrupts = <2 7 0>;
			interrupt-parent = <&mpc5200_pic>;
		};

		i2c@3d00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5200-i2c","fsl-i2c";
			cell-index = <0>;
			reg = <3d00 40>;
			interrupts = <2 f 0>;
			interrupt-parent = <&mpc5200_pic>;
			fsl5200-clocking;
		};

		i2c@3d40 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,mpc5200-i2c","fsl-i2c";
			cell-index = <1>;
			reg = <3d40 40>;
			interrupts = <2 10 0>;
			interrupt-parent = <&mpc5200_pic>;
			fsl5200-clocking;
		};
		sram@8000 {
			compatible = "fsl,mpc5200-sram","sram";
			reg = <8000 4000>;
		};
	};

	pci@f0000d00 {
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		device_type = "pci";
		compatible = "fsl,mpc5200-pci";
		reg = <f0000d00 100>;
		interrupt-map-mask = <f800 0 0 7>;
		interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3
				 c000 0 0 2 &mpc5200_pic 0 0 3
				 c000 0 0 3 &mpc5200_pic 0 0 3
				 c000 0 0 4 &mpc5200_pic 0 0 3>;
		clock-frequency = <0>; // From boot loader
		interrupts = <2 8 0 2 9 0 2 a 0>;
		interrupt-parent = <&mpc5200_pic>;
		bus-range = <0 0>;
		ranges = <42000000 0 80000000 80000000 0 20000000
			  02000000 0 a0000000 a0000000 0 10000000
			  01000000 0 00000000 b0000000 0 01000000>;
	};
};