MIPS: mm: XBurst CPU requires sync after DMA
I am not sure why this is required, but if this is not enabled, reading
from a buffer in which data has been DMA'd may read incorrect values.
This used to happen for instance in mmc_app_send_scr()
(drivers/mmc/core/sd_ops.c), where data is DMA'd to a buffer then copied
by the CPU to a different location.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index baa4ea9..7badc40 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -112,6 +112,7 @@
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_ZBOOT
select DMA_NONCOHERENT
+ select ARCH_HAS_SYNC_DMA_FOR_CPU
select IRQ_MIPS_CPU
select PINCTRL
select GPIOLIB
