commit 16bd395259cf3e9966d40478891e0e610da109d4
author Peter Ujfalusi <peter.ujfalusi@ti.com> Thu Jun 04 16:04:20 2015 +0300
committer Mark Brown <broonie@kernel.org> Thu Jun 04 17:50:03 2015 +0100
tree 6b606554b6144aa7ecce151ca92ce55a63028f23
parent dd6e3053405c2fe7baa36e4fe2a12083f508abfc

ASoC: tas2552: Rename mclk parameter to pll_clkin to match with the datasheet

MCLK is one of the possible source for the pll_clkin frequency. Make this
clear by renaming the variable.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

sound/soc/codecs/tas2552.c

diff --git a/sound/soc/codecs/tas2552.c b/sound/soc/codecs/tas2552.c
index 61419e2..e29b29b 100644
--- a/sound/soc/codecs/tas2552.c
+++ b/sound/soc/codecs/tas2552.c
@@ -75,7 +75,7 @@
 	struct regulator_bulk_data supplies[TAS2552_NUM_SUPPLIES];
 	struct gpio_desc *enable_gpio;
 	unsigned char regs[TAS2552_VBAT_DATA];
-	unsigned int mclk;
+	unsigned int pll_clkin;
 };
 
 /* Input mux controls */
@@ -141,13 +141,13 @@
 	int d;
 	u8 p, j;
 
-	if (!tas2552->mclk)
+	if (!tas2552->pll_clkin)
 		return -EINVAL;
 
 	snd_soc_update_bits(codec, TAS2552_CFG_2, TAS2552_PLL_ENABLE, 0);
 
-	if (tas2552->mclk == TAS2552_245MHZ_CLK ||
-		tas2552->mclk == TAS2552_225MHZ_CLK) {
+	if (tas2552->pll_clkin == TAS2552_245MHZ_CLK ||
+	    tas2552->pll_clkin == TAS2552_225MHZ_CLK) {
 		/* By pass the PLL configuration */
 		snd_soc_update_bits(codec, TAS2552_PLL_CTRL_2,
 				    TAS2552_PLL_BYPASS_MASK,
@@ -171,8 +171,8 @@
 			return -EINVAL;
 		}
 
-		j = (pll_clk * 2 * (1 << p)) / tas2552->mclk;
-		d = (pll_clk * 2 * (1 << p)) % tas2552->mclk;
+		j = (pll_clk * 2 * (1 << p)) / tas2552->pll_clkin;
+		d = (pll_clk * 2 * (1 << p)) % tas2552->pll_clkin;
 
 		snd_soc_update_bits(codec, TAS2552_PLL_CTRL_1,
 				TAS2552_PLL_J_MASK, j);
@@ -245,7 +245,7 @@
 	struct snd_soc_codec *codec = dai->codec;
 	struct tas2552_data *tas2552 = dev_get_drvdata(codec->dev);
 
-	tas2552->mclk = freq;
+	tas2552->pll_clkin = freq;
 
 	return 0;
 }