Qualcomm Technologies EMAC Gigabit Ethernet Controller

This network controller consists of two devices: a MAC and an SGMII
internal PHY.  Each device is represented by a device tree node.  A phandle
connects the MAC node to its corresponding internal phy node.  Another
phandle points to the external PHY node.

Required properties:

MAC node:
- compatible : Should be "qcom,fsm9900-emac".
- reg : Offset and length of the register regions for the device
- interrupts : Interrupt number used by this controller
- mac-address : The 6-byte MAC address. If present, it is the default
	MAC address.
- internal-phy : phandle to the internal PHY node
- phy-handle : phandle to the external PHY node

Internal PHY node:
- compatible : Should be "qcom,fsm9900-emac-sgmii" or "qcom,qdf2432-emac-sgmii".
- reg : Offset and length of the register region(s) for the device
- interrupts : Interrupt number used by this controller

The external phy child node:
- reg : The phy address

Example:

FSM9900:

soc {
	#address-cells = <1>;
	#size-cells = <1>;

	emac0: ethernet@feb20000 {
		compatible = "qcom,fsm9900-emac";
		reg = <0xfeb20000 0x10000>,
		      <0xfeb36000 0x1000>;
		interrupts = <76>;

		clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>,
			<&gcc 6>, <&gcc 7>;
		clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk",
			"mdio_clk", "tx_clk", "rx_clk", "sys_clk";

		internal-phy = <&emac_sgmii>;

		phy-handle = <&phy0>;

		#address-cells = <1>;
		#size-cells = <0>;
		phy0: ethernet-phy@0 {
			reg = <0>;
		};

		pinctrl-names = "default";
		pinctrl-0 = <&mdio_pins_a>;
	};

	emac_sgmii: ethernet@feb38000 {
		compatible = "qcom,fsm9900-emac-sgmii";
		reg = <0xfeb38000 0x1000>;
		interrupts = <80>;
	};

	tlmm: pinctrl@fd510000 {
		compatible = "qcom,fsm9900-pinctrl";

		mdio_pins_a: mdio {
			state {
				pins = "gpio123", "gpio124";
				function = "mdio";
			};
		};
	};


QDF2432:

soc {
	#address-cells = <2>;
	#size-cells = <2>;

	emac0: ethernet@38800000 {
		compatible = "qcom,fsm9900-emac";
		reg = <0x0 0x38800000 0x0 0x10000>,
		      <0x0 0x38816000 0x0 0x1000>;
		interrupts = <0 256 4>;

		clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>,
			 <&gcc 6>, <&gcc 7>;
		clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk",
			"mdio_clk", "tx_clk", "rx_clk", "sys_clk";

		internal-phy = <&emac_sgmii>;

		phy-handle = <&phy0>;

		#address-cells = <1>;
		#size-cells = <0>;
		phy0: ethernet-phy@4 {
			reg = <4>;
		};
	};

	emac_sgmii: ethernet@410400 {
		compatible = "qcom,qdf2432-emac-sgmii";
		reg = <0x0 0x00410400 0x0 0xc00>, /* Base address */
		      <0x0 0x00410000 0x0 0x400>; /* Per-lane digital */
		interrupts = <0 254 1>;
	};