tree 10ee30114c0333feed5b80bffb571d9b935c70d0
parent 44ab8cc56c45ca781371a4a77f35da19cf5db028
author Ben Skeggs <bskeggs@redhat.com> 1328572794 +1000
committer Ben Skeggs <bskeggs@redhat.com> 1331622898 +1000

drm/nvc0/pm: restrict pll mode to clocks that can actually use it

Fixes reclocking failure on some chips where we attempted to set PDAEMON
to PLL mode.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>