| commit | 1db18260f15315e206469391d5b5e3427be55ad3 | [log] [tgz] |
|---|---|---|
| author | Jani Nikula <jani.nikula@intel.com> | Mon Aug 23 19:18:10 2021 +0300 |
| committer | Jani Nikula <jani.nikula@intel.com> | Tue Aug 24 11:02:31 2021 +0300 |
| tree | 3673431cbe55baa472996a95f06e364d38df7a21 | |
| parent | 59821ed9c4a63de051042d71526d7bb4eac0617b [diff] |
drm/i915/dg2: add TRANS_DP2_VFREQHIGH and TRANS_DP2_VFREQLOW Add the registers for specifying the lower and higher 24 bits of the DP 2.0 pixel clock frequency in Hz. Bspec: 53326 Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/9047f10318a30bc03ce8516ee3f5512437a95663.1629735412.git.jani.nikula@intel.com