/dts-v1/;
/*
 * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
 *
 * This device tree is pruned and patched by early boot code before
 * use.  Because of this, it contains a super-set of the available
 * devices and properties.
 */
/ {
	compatible = "cavium,octeon-3860";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&ciu>;

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges; /* Direct mapping */

		ciu: interrupt-controller@1070000000000 {
			compatible = "cavium,octeon-3860-ciu";
			interrupt-controller;
			/* Interrupts are specified by two parts:
			 * 1) Controller register (0 or 1)
			 * 2) Bit within the register (0..63)
			 */
			#interrupt-cells = <2>;
			reg = <0x10700 0x00000000 0x0 0x7000>;
		};

		gpio: gpio-controller@1070000000800 {
			#gpio-cells = <2>;
			compatible = "cavium,octeon-3860-gpio";
			reg = <0x10700 0x00000800 0x0 0x100>;
			gpio-controller;
			/* Interrupts are specified by two parts:
			 * 1) GPIO pin number (0..15)
			 * 2) Triggering (1 - edge rising
			 *		  2 - edge falling
			 *		  4 - level active high
			 *		  8 - level active low)
			 */
			interrupt-controller;
			#interrupt-cells = <2>;
			/* The GPIO pin connect to 16 consecutive CUI bits */
			interrupts = <0 16>, <0 17>, <0 18>, <0 19>,
				     <0 20>, <0 21>, <0 22>, <0 23>,
				     <0 24>, <0 25>, <0 26>, <0 27>,
				     <0 28>, <0 29>, <0 30>, <0 31>;
		};

		smi0: mdio@1180000001800 {
			compatible = "cavium,octeon-3860-mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x11800 0x00001800 0x0 0x40>;

			phy0: ethernet-phy@0 {
				compatible = "marvell,88e1118";
				marvell,reg-init =
					/* Fix rx and tx clock transition timing */
					<2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
					/* Adjust LED drive. */
					<3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
					/* irq, blink-activity, blink-link */
					<3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
				reg = <0>;
			};

			phy1: ethernet-phy@1 {
				compatible = "marvell,88e1118";
				marvell,reg-init =
					/* Fix rx and tx clock transition timing */
					<2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
					/* Adjust LED drive. */
					<3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
					/* irq, blink-activity, blink-link */
					<3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
				reg = <1>;
			};

			phy2: ethernet-phy@2 {
				reg = <2>;
				compatible = "marvell,88e1149r";
				marvell,reg-init = <3 0x10 0 0x5777>,
					<3 0x11 0 0x00aa>,
					<3 0x12 0 0x4105>,
					<3 0x13 0 0x0a60>;
			};
			phy3: ethernet-phy@3 {
				reg = <3>;
				compatible = "marvell,88e1149r";
				marvell,reg-init = <3 0x10 0 0x5777>,
					<3 0x11 0 0x00aa>,
					<3 0x12 0 0x4105>,
					<3 0x13 0 0x0a60>;
			};
			phy4: ethernet-phy@4 {
				reg = <4>;
				compatible = "marvell,88e1149r";
				marvell,reg-init = <3 0x10 0 0x5777>,
					<3 0x11 0 0x00aa>,
					<3 0x12 0 0x4105>,
					<3 0x13 0 0x0a60>;
			};
			phy5: ethernet-phy@5 {
				reg = <5>;
				compatible = "marvell,88e1149r";
				marvell,reg-init = <3 0x10 0 0x5777>,
					<3 0x11 0 0x00aa>,
					<3 0x12 0 0x4105>,
					<3 0x13 0 0x0a60>;
			};

			phy6: ethernet-phy@6 {
				reg = <6>;
				compatible = "marvell,88e1149r";
				marvell,reg-init = <3 0x10 0 0x5777>,
					<3 0x11 0 0x00aa>,
					<3 0x12 0 0x4105>,
					<3 0x13 0 0x0a60>;
			};
			phy7: ethernet-phy@7 {
				reg = <7>;
				compatible = "marvell,88e1149r";
				marvell,reg-init = <3 0x10 0 0x5777>,
					<3 0x11 0 0x00aa>,
					<3 0x12 0 0x4105>,
					<3 0x13 0 0x0a60>;
			};
			phy8: ethernet-phy@8 {
				reg = <8>;
				compatible = "marvell,88e1149r";
				marvell,reg-init = <3 0x10 0 0x5777>,
					<3 0x11 0 0x00aa>,
					<3 0x12 0 0x4105>,
					<3 0x13 0 0x0a60>;
			};
			phy9: ethernet-phy@9 {
				reg = <9>;
				compatible = "marvell,88e1149r";
				marvell,reg-init = <3 0x10 0 0x5777>,
					<3 0x11 0 0x00aa>,
					<3 0x12 0 0x4105>,
					<3 0x13 0 0x0a60>;
			};
		};

		smi1: mdio@1180000001900 {
			compatible = "cavium,octeon-3860-mdio";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x11800 0x00001900 0x0 0x40>;

			phy100: ethernet-phy@1 {
				reg = <1>;
				compatible = "marvell,88e1149r";
				marvell,reg-init = <3 0x10 0 0x5777>,
					<3 0x11 0 0x00aa>,
					<3 0x12 0 0x4105>,
					<3 0x13 0 0x0a60>;
				interrupt-parent = <&gpio>;
				interrupts = <12 8>; /* Pin 12, active low */
			};
			phy101: ethernet-phy@2 {
				reg = <2>;
				compatible = "marvell,88e1149r";
				marvell,reg-init = <3 0x10 0 0x5777>,
					<3 0x11 0 0x00aa>,
					<3 0x12 0 0x4105>,
					<3 0x13 0 0x0a60>;
				interrupt-parent = <&gpio>;
				interrupts = <12 8>; /* Pin 12, active low */
			};
			phy102: ethernet-phy@3 {
				reg = <3>;
				compatible = "marvell,88e1149r";
				marvell,reg-init = <3 0x10 0 0x5777>,
					<3 0x11 0 0x00aa>,
					<3 0x12 0 0x4105>,
					<3 0x13 0 0x0a60>;
				interrupt-parent = <&gpio>;
				interrupts = <12 8>; /* Pin 12, active low */
			};
			phy103: ethernet-phy@4 {
				reg = <4>;
				compatible = "marvell,88e1149r";
				marvell,reg-init = <3 0x10 0 0x5777>,
					<3 0x11 0 0x00aa>,
					<3 0x12 0 0x4105>,
					<3 0x13 0 0x0a60>;
				interrupt-parent = <&gpio>;
				interrupts = <12 8>; /* Pin 12, active low */
			};
		};

		mix0: ethernet@1070000100000 {
			compatible = "cavium,octeon-5750-mix";
			reg = <0x10700 0x00100000 0x0 0x100>, /* MIX */
			      <0x11800 0xE0000000 0x0 0x300>, /* AGL */
			      <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED  */
			      <0x11800 0xE0002000 0x0 0x8>;   /* AGL_PRT_CTL */
			cell-index = <0>;
			interrupts = <0 62>, <1 46>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			phy-handle = <&phy0>;
		};

		mix1: ethernet@1070000100800 {
			compatible = "cavium,octeon-5750-mix";
			reg = <0x10700 0x00100800 0x0 0x100>, /* MIX */
			      <0x11800 0xE0000800 0x0 0x300>, /* AGL */
			      <0x11800 0xE0000400 0x0 0x400>, /* AGL_SHARED  */
			      <0x11800 0xE0002008 0x0 0x8>;   /* AGL_PRT_CTL */
			cell-index = <1>;
			interrupts = <1 18>, < 1 46>;
			local-mac-address = [ 00 00 00 00 00 00 ];
			phy-handle = <&phy1>;
		};

		pip: pip@11800a0000000 {
			compatible = "cavium,octeon-3860-pip";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x11800 0xa0000000 0x0 0x2000>;

			interface@0 {
				compatible = "cavium,octeon-3860-pip-interface";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0>; /* interface */

				ethernet@0 {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0x0>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
					phy-handle = <&phy2>;
					cavium,alt-phy-handle = <&phy100>;
				};
				ethernet@1 {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0x1>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
					phy-handle = <&phy3>;
					cavium,alt-phy-handle = <&phy101>;
				};
				ethernet@2 {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0x2>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
					phy-handle = <&phy4>;
					cavium,alt-phy-handle = <&phy102>;
				};
				ethernet@3 {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0x3>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
					phy-handle = <&phy5>;
					cavium,alt-phy-handle = <&phy103>;
				};
				ethernet@4 {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0x4>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
				};
				ethernet@5 {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0x5>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
				};
				ethernet@6 {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0x6>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
				};
				ethernet@7 {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0x7>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
				};
				ethernet@8 {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0x8>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
				};
				ethernet@9 {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0x9>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
				};
				ethernet@a {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0xa>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
				};
				ethernet@b {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0xb>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
				};
				ethernet@c {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0xc>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
				};
				ethernet@d {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0xd>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
				};
				ethernet@e {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0xe>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
				};
				ethernet@f {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0xf>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
				};
			};

			interface@1 {
				compatible = "cavium,octeon-3860-pip-interface";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <1>; /* interface */

				ethernet@0 {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0x0>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
					phy-handle = <&phy6>;
				};
				ethernet@1 {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0x1>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
					phy-handle = <&phy7>;
				};
				ethernet@2 {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0x2>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
					phy-handle = <&phy8>;
				};
				ethernet@3 {
					compatible = "cavium,octeon-3860-pip-port";
					reg = <0x3>; /* Port */
					local-mac-address = [ 00 00 00 00 00 00 ];
					phy-handle = <&phy9>;
				};
			};
		};

		twsi0: i2c@1180000001000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "cavium,octeon-3860-twsi";
			reg = <0x11800 0x00001000 0x0 0x200>;
			interrupts = <0 45>;
			clock-frequency = <100000>;

			rtc@68 {
				compatible = "dallas,ds1337";
				reg = <0x68>;
			};
			tmp@4c {
				compatible = "ti,tmp421";
				reg = <0x4c>;
			};
		};

		twsi1: i2c@1180000001200 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "cavium,octeon-3860-twsi";
			reg = <0x11800 0x00001200 0x0 0x200>;
			interrupts = <0 59>;
			clock-frequency = <100000>;
		};

		uart0: serial@1180000000800 {
			compatible = "cavium,octeon-3860-uart","ns16550";
			reg = <0x11800 0x00000800 0x0 0x400>;
			clock-frequency = <0>;
			current-speed = <115200>;
			reg-shift = <3>;
			interrupts = <0 34>;
		};

		uart1: serial@1180000000c00 {
			compatible = "cavium,octeon-3860-uart","ns16550";
			reg = <0x11800 0x00000c00 0x0 0x400>;
			clock-frequency = <0>;
			current-speed = <115200>;
			reg-shift = <3>;
			interrupts = <0 35>;
		};

		uart2: serial@1180000000400 {
			compatible = "cavium,octeon-3860-uart","ns16550";
			reg = <0x11800 0x00000400 0x0 0x400>;
			clock-frequency = <0>;
			current-speed = <115200>;
			reg-shift = <3>;
			interrupts = <1 16>;
		};

		bootbus: bootbus@1180000000000 {
			compatible = "cavium,octeon-3860-bootbus";
			reg = <0x11800 0x00000000 0x0 0x200>;
			/* The chip select number and offset */
			#address-cells = <2>;
			/* The size of the chip select region */
			#size-cells = <1>;
			ranges = <0 0  0x0 0x1f400000  0xc00000>,
				 <1 0  0x10000 0x30000000  0>,
				 <2 0  0x10000 0x40000000  0>,
				 <3 0  0x10000 0x50000000  0>,
				 <4 0  0x0 0x1d020000  0x10000>,
				 <5 0  0x0 0x1d040000  0x10000>,
				 <6 0  0x0 0x1d050000  0x10000>,
				 <7 0  0x10000 0x90000000  0>;

			cavium,cs-config@0 {
				compatible = "cavium,octeon-3860-bootbus-config";
				cavium,cs-index = <0>;
				cavium,t-adr  = <20>;
				cavium,t-ce   = <60>;
				cavium,t-oe   = <60>;
				cavium,t-we   = <45>;
				cavium,t-rd-hld = <35>;
				cavium,t-wr-hld = <45>;
				cavium,t-pause  = <0>;
				cavium,t-wait   = <0>;
				cavium,t-page   = <35>;
				cavium,t-rd-dly = <0>;

				cavium,pages     = <0>;
				cavium,bus-width = <8>;
			};
			cavium,cs-config@4 {
				compatible = "cavium,octeon-3860-bootbus-config";
				cavium,cs-index = <4>;
				cavium,t-adr  = <320>;
				cavium,t-ce   = <320>;
				cavium,t-oe   = <320>;
				cavium,t-we   = <320>;
				cavium,t-rd-hld = <320>;
				cavium,t-wr-hld = <320>;
				cavium,t-pause  = <320>;
				cavium,t-wait   = <320>;
				cavium,t-page   = <320>;
				cavium,t-rd-dly = <0>;

				cavium,pages     = <0>;
				cavium,bus-width = <8>;
			};
			cavium,cs-config@5 {
				compatible = "cavium,octeon-3860-bootbus-config";
				cavium,cs-index = <5>;
				cavium,t-adr  = <5>;
				cavium,t-ce   = <300>;
				cavium,t-oe   = <125>;
				cavium,t-we   = <150>;
				cavium,t-rd-hld = <100>;
				cavium,t-wr-hld = <30>;
				cavium,t-pause  = <0>;
				cavium,t-wait   = <30>;
				cavium,t-page   = <320>;
				cavium,t-rd-dly = <0>;

				cavium,pages     = <0>;
				cavium,bus-width = <16>;
			};
			cavium,cs-config@6 {
				compatible = "cavium,octeon-3860-bootbus-config";
				cavium,cs-index = <6>;
				cavium,t-adr  = <5>;
				cavium,t-ce   = <300>;
				cavium,t-oe   = <270>;
				cavium,t-we   = <150>;
				cavium,t-rd-hld = <100>;
				cavium,t-wr-hld = <70>;
				cavium,t-pause  = <0>;
				cavium,t-wait   = <0>;
				cavium,t-page   = <320>;
				cavium,t-rd-dly = <0>;

				cavium,pages     = <0>;
				cavium,wait-mode;
				cavium,bus-width = <16>;
			};

			flash0: nor@0,0 {
				compatible = "cfi-flash";
				reg = <0 0 0x800000>;
				#address-cells = <1>;
				#size-cells = <1>;
			};

			led0: led-display@4,0 {
				compatible = "avago,hdsp-253x";
				reg = <4 0x20 0x20>, <4 0 0x20>;
			};

			cf0: compact-flash@5,0 {
				compatible = "cavium,ebt3000-compact-flash";
				reg = <5 0 0x10000>, <6 0 0x10000>;
				cavium,bus-width = <16>;
				cavium,true-ide;
				cavium,dma-engine-handle = <&dma0>;
			};
		};

		dma0: dma-engine@1180000000100 {
			compatible = "cavium,octeon-5750-bootbus-dma";
			reg = <0x11800 0x00000100 0x0 0x8>;
			interrupts = <0 63>;
		};
		dma1: dma-engine@1180000000108 {
			compatible = "cavium,octeon-5750-bootbus-dma";
			reg = <0x11800 0x00000108 0x0 0x8>;
			interrupts = <0 63>;
		};

		uctl: uctl@118006f000000 {
			compatible = "cavium,octeon-6335-uctl";
			reg = <0x11800 0x6f000000 0x0 0x100>;
			ranges; /* Direct mapping */
			#address-cells = <2>;
			#size-cells = <2>;
			/* 12MHz, 24MHz and 48MHz allowed */
			refclk-frequency = <12000000>;
			/* Either "crystal" or "external" */
			refclk-type = "crystal";

			ehci@16f0000000000 {
				compatible = "cavium,octeon-6335-ehci","usb-ehci";
				reg = <0x16f00 0x00000000 0x0 0x100>;
				interrupts = <0 56>;
				big-endian-regs;
			};
			ohci@16f0000000400 {
				compatible = "cavium,octeon-6335-ohci","usb-ohci";
				reg = <0x16f00 0x00000400 0x0 0x100>;
				interrupts = <0 56>;
				big-endian-regs;
			};
		};
	};

	aliases {
		mix0 = &mix0;
		mix1 = &mix1;
		pip = &pip;
		smi0 = &smi0;
		smi1 = &smi1;
		twsi0 = &twsi0;
		twsi1 = &twsi1;
		uart0 = &uart0;
		uart1 = &uart1;
		uart2 = &uart2;
		flash0 = &flash0;
		cf0 = &cf0;
		uctl = &uctl;
		led0 = &led0;
	};
 };