| commit | f68cbb35788e3d4e76638e4cc4cc1df9cac03587 | [log] [tgz] |
|---|---|---|
| author | Sowjanya Komatineni <skomatineni@nvidia.com> | Fri Aug 16 12:41:58 2019 -0700 |
| committer | Thierry Reding <treding@nvidia.com> | Mon Nov 11 14:53:03 2019 +0100 |
| tree | 829932ccff4e39999af322a3e04db6acec2b71a1 | |
| parent | a99d744d8c9ca7e00adeb14dd11971b4b5b8271f [diff] |
clk: tegra: Use fence_udelay() during PLLU init This patch uses fence_udelay rather than udelay during PLLU initialization to ensure writes to clock registers happens before waiting for specified delay. Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>