commit 33c7c7b7f2eb76520cd8ddcb7fe458383783e0f8
author Felipe Balbi <balbi@ti.com> Mon Sep 08 17:54:32 2014 -0700
committer Tony Lindgren <tony@atomide.com> Thu Sep 11 13:03:32 2014 -0700
tree f382de715f31508b3cfe9c227014bc64efe5f211
parent 176da6c766ce3d5d8c88a7afdaefcc5fd6d8afac

arm: omap: irq: define INTC_ILR0 register

this is currently used as a hardcoded 0x100
offset.

Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

arch/arm/mach-omap2/irq.c

diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index ae082c6..bae0329 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -41,6 +41,7 @@
 #define INTC_MIR_CLEAR0		0x0088
 #define INTC_MIR_SET0		0x008c
 #define INTC_PENDING_IRQ0	0x0098
+#define INTC_ILR0		0x0100
 /* Number of IRQ state bits in each MIR register */
 #define IRQ_BITS_PER_REG	32