clk: exynos5250: add clock ID for div_pcm0
There is no gate for the PCM clock input to the AudioSS block, so
the parent of sclk_pcm is div_pcm0. Add a clock ID for it so that
we can reference it in device trees.
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
index 5883ec8..492ed09 100644
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
@@ -62,6 +62,7 @@
div_i2s1 157
div_i2s2 158
sclk_hdmiphy 159
+ div_pcm0 160
[Peripheral Clock Gates]
diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 25c77ab..ff4beeb 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -329,7 +329,7 @@
DIV(0, "div_jpeg", "mout_jpeg", DIV_GEN, 4, 4),
DIV(0, "div_audio0", "mout_audio0", DIV_MAU, 0, 4),
- DIV(0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
+ DIV(CLK_DIV_PCM0, "div_pcm0", "sclk_audio0", DIV_MAU, 4, 8),
DIV(0, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
DIV(0, "div_usb3", "mout_usb3", DIV_FSYS0, 24, 4),
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
index 0512572..922f2dc 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -55,6 +55,7 @@
#define CLK_DIV_I2S1 157
#define CLK_DIV_I2S2 158
#define CLK_SCLK_HDMIPHY 159
+#define CLK_DIV_PCM0 160
/* gate clocks */
#define CLK_GSCL0 256
