| commit | 35817d34bd07b4e1cd597e054fa2bd9c9c111aab | [log] [tgz] |
|---|---|---|
| author | Icenowy Zheng <icenowy@aosc.io> | Fri Mar 16 22:02:09 2018 +0800 |
| committer | Linus Walleij <linus.walleij@linaro.org> | Tue Mar 27 15:07:49 2018 +0200 |
| tree | 4e0c17938c4a90cff2b3f1dbe127d5760629b7d8 | |
| parent | 29dfc6bbcc5e1ef7ce1008c4713387efb8f567d2 [diff] |
pinctrl: sunxi: change irq_bank_base to irq_bank_map The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Change the current code that uses IRQ bank base to a IRQ bank map, in order to support the case that holes exist among IRQ banks. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>