tree ccf33dc79ca03ac4563c4c3b0e678823f03e6e9c
parent 390227dca870cd0b8b0961da9e293551015c0007
author Claudiu Beznea <claudiu.beznea@microchip.com> 1595403494 +0300
committer Stephen Boyd <sboyd@kernel.org> 1595582327 -0700

clk: at91: sam9x60-pll: use frac when setting frequency

In commit a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
the fractional part of PLL wasn't set on registers but it was
calculated and taken into account for determining div and mul
(see sam9x60_pll_get_best_div_mul()).

Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-7-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>