commit 372ab3bc3711db46ae1205401c2aac2ed16fc348
author Dan Williams <dan.j.williams@intel.com> Mon Dec 05 20:28:34 2022 -0800
committer Dan Williams <dan.j.williams@intel.com> Tue Dec 06 14:37:52 2022 -0800
tree 340d9c7d16ea006c6155ca8c3a7169341e1a72ef
parent 7fe898041fb0c8e630504ecc2cb8805651ac85c1

cxl/pci: Add some type-safety to the AER trace points

The first argument to the CXL AER trace points is the source device.
Pass a 'const struct device *' rather than a 'const char *' for more
type precision / safety.

Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Dave Jiang <dave.jiang@intel.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Link: https://lore.kernel.org/r/167030091477.4045167.15174636482098463885.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

drivers/cxl/pci.c

diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index 6cec9fa..cced4a0 100644
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -562,7 +562,7 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds)
 	}
 
 	header_log_copy(cxlds, hl);
-	trace_cxl_aer_uncorrectable_error(dev_name(dev), status, fe, hl);
+	trace_cxl_aer_uncorrectable_error(dev, status, fe, hl);
 	writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);
 
 	return true;
@@ -644,7 +644,7 @@ static void cxl_cor_error_detected(struct pci_dev *pdev)
 	status = le32_to_cpu(readl(addr));
 	if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {
 		writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);
-		trace_cxl_aer_correctable_error(dev_name(dev), status);
+		trace_cxl_aer_correctable_error(dev, status);
 	}
 }
 

include/trace/events/cxl.h

diff --git a/include/trace/events/cxl.h b/include/trace/events/cxl.h
index 72c3e28..ad085a2 100644
--- a/include/trace/events/cxl.h
+++ b/include/trace/events/cxl.h
@@ -45,16 +45,16 @@
 )
 
 TRACE_EVENT(cxl_aer_uncorrectable_error,
-	TP_PROTO(const char *dev_name, u32 status, u32 fe, u32 *hl),
-	TP_ARGS(dev_name, status, fe, hl),
+	TP_PROTO(const struct device *dev, u32 status, u32 fe, u32 *hl),
+	TP_ARGS(dev, status, fe, hl),
 	TP_STRUCT__entry(
-		__string(dev_name, dev_name)
+		__string(dev_name, dev_name(dev))
 		__field(u32, status)
 		__field(u32, first_error)
 		__array(u32, header_log, CXL_HEADERLOG_SIZE_U32)
 	),
 	TP_fast_assign(
-		__assign_str(dev_name, dev_name);
+		__assign_str(dev_name, dev_name(dev));
 		__entry->status = status;
 		__entry->first_error = fe;
 		/*
@@ -89,14 +89,14 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,
 )
 
 TRACE_EVENT(cxl_aer_correctable_error,
-	TP_PROTO(const char *dev_name, u32 status),
-	TP_ARGS(dev_name, status),
+	TP_PROTO(const struct device *dev, u32 status),
+	TP_ARGS(dev, status),
 	TP_STRUCT__entry(
-		__string(dev_name, dev_name)
+		__string(dev_name, dev_name(dev))
 		__field(u32, status)
 	),
 	TP_fast_assign(
-		__assign_str(dev_name, dev_name);
+		__assign_str(dev_name, dev_name(dev));
 		__entry->status = status;
 	),
 	TP_printk("%s: status: '%s'",