tree de8343016b397fb64726093a993ae35a80a056a1
parent 1bef0986b125942d65d39c10cbfa75b20c3b94b3
author Claudiu Beznea <claudiu.beznea@microchip.com> 1595403493 +0300
committer Stephen Boyd <sboyd@kernel.org> 1595582327 -0700

clk: at91: sam9x60-pll: check fcore against ranges

According to datasheet the range of 600-1200MHz is for the
frequency generated by the fractional part of the PLL (namely
Fcorepllck according to datasheet). With this in mind the output
range of the PLL itself (fractional + div), taking into account
that the divider is 8 bits wide, is 600/256-1200Hz=2.3-1200MHz.

Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-6-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>