| commit | 3b756ccddb8a75563900cd603c83160b43f3d691 | [log] [tgz] |
|---|---|---|
| author | Guo Ren <guoren@linux.alibaba.com> | Thu Dec 24 05:59:57 2020 +0000 |
| committer | Guo Ren <guoren@linux.alibaba.com> | Tue Jan 12 09:52:41 2021 +0800 |
| tree | af6428140af2760616d577a0b1e515a45b58207c | |
| parent | c109f42450ec25283169dd6c0acce8d053493732 [diff] |
csky: Fix TLB maintenance synchronization problem TLB invalidate didn't contain a barrier operation in csky cpu and we need to prevent previous PTW response after TLB invalidation instruction. Of cause, the ASID changing also needs to take care of the issue. CPU0 CPU1 =============== =============== set_pte sync_is() -> See the previous set_pte for all harts tlbi.vas -> Invalidate all harts TLB entry & flush pipeline Signed-off-by: Guo Ren <guoren@linux.alibaba.com>