x86: correct register constraints for 64-bit atomic operations
x86_64 add/sub atomic ops does not seems to accept integer values bigger
than 32 bits as immediates. Intel's add/sub documentation specifies they
have to be passed as registers.
The only operations in the x86-64 architecture which accept arbitrary
64-bit immediates is "movq" to any register; similarly, the only
operation which accept arbitrary 64-bit displacement is "movabs" to or
from al/ax/eax/rax.
http://gcc.gnu.org/onlinedocs/gcc-4.3.0/gcc/Machine-Constraints.html
states :
e
32-bit signed integer constant, or a symbolic reference known to fit
that range (for immediate operands in sign-extending x86-64
instructions).
Z
32-bit unsigned integer constant, or a symbolic reference known to
fit that range (for immediate operands in zero-extending x86-64
instructions).
Since add/sub does sign extension, using the "e" constraint seems appropriate.
It applies to 2.6.27-rc, 2.6.26, 2.6.25...
Signed-off-by: Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
diff --git a/include/asm-x86/atomic_64.h b/include/asm-x86/atomic_64.h
index a009519..91c7d03 100644
--- a/include/asm-x86/atomic_64.h
+++ b/include/asm-x86/atomic_64.h
@@ -228,7 +228,7 @@
{
asm volatile(LOCK_PREFIX "addq %1,%0"
: "=m" (v->counter)
- : "ir" (i), "m" (v->counter));
+ : "er" (i), "m" (v->counter));
}
/**
@@ -242,7 +242,7 @@
{
asm volatile(LOCK_PREFIX "subq %1,%0"
: "=m" (v->counter)
- : "ir" (i), "m" (v->counter));
+ : "er" (i), "m" (v->counter));
}
/**
@@ -260,7 +260,7 @@
asm volatile(LOCK_PREFIX "subq %2,%0; sete %1"
: "=m" (v->counter), "=qm" (c)
- : "ir" (i), "m" (v->counter) : "memory");
+ : "er" (i), "m" (v->counter) : "memory");
return c;
}
@@ -341,7 +341,7 @@
asm volatile(LOCK_PREFIX "addq %2,%0; sets %1"
: "=m" (v->counter), "=qm" (c)
- : "ir" (i), "m" (v->counter) : "memory");
+ : "er" (i), "m" (v->counter) : "memory");
return c;
}
