| // SPDX-License-Identifier: GPL-2.0 |
| |
| /* |
| * Copyright 2020-2022 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| */ |
| |
| #include "gaudi2P.h" |
| #include "gaudi2_masks.h" |
| #include "../include/gaudi2/gaudi2_special_blocks.h" |
| #include "../include/hw_ip/mmu/mmu_general.h" |
| #include "../include/hw_ip/mmu/mmu_v2_0.h" |
| #include "../include/gaudi2/gaudi2_packets.h" |
| #include "../include/gaudi2/gaudi2_reg_map.h" |
| #include "../include/gaudi2/gaudi2_async_ids_map_extended.h" |
| #include "../include/gaudi2/arc/gaudi2_arc_common_packets.h" |
| |
| #include <linux/module.h> |
| #include <linux/pci.h> |
| #include <linux/hwmon.h> |
| #include <linux/iommu.h> |
| |
| #define GAUDI2_DMA_POOL_BLK_SIZE SZ_256 /* 256 bytes */ |
| |
| #define GAUDI2_RESET_TIMEOUT_MSEC 2000 /* 2000ms */ |
| |
| #define GAUDI2_RESET_POLL_TIMEOUT_USEC 500000 /* 500ms */ |
| #define GAUDI2_PLDM_HRESET_TIMEOUT_MSEC 25000 /* 25s */ |
| #define GAUDI2_PLDM_SRESET_TIMEOUT_MSEC 25000 /* 25s */ |
| #define GAUDI2_PLDM_RESET_POLL_TIMEOUT_USEC 3000000 /* 3s */ |
| #define GAUDI2_RESET_POLL_CNT 3 |
| #define GAUDI2_RESET_WAIT_MSEC 1 /* 1ms */ |
| #define GAUDI2_CPU_RESET_WAIT_MSEC 100 /* 100ms */ |
| #define GAUDI2_PLDM_RESET_WAIT_MSEC 1000 /* 1s */ |
| #define GAUDI2_CB_POOL_CB_CNT 512 |
| #define GAUDI2_CB_POOL_CB_SIZE SZ_128K /* 128KB */ |
| #define GAUDI2_MSG_TO_CPU_TIMEOUT_USEC 4000000 /* 4s */ |
| #define GAUDI2_WAIT_FOR_BL_TIMEOUT_USEC 25000000 /* 25s */ |
| #define GAUDI2_TEST_QUEUE_WAIT_USEC 100000 /* 100ms */ |
| #define GAUDI2_PLDM_TEST_QUEUE_WAIT_USEC 1000000 /* 1s */ |
| |
| #define GAUDI2_ALLOC_CPU_MEM_RETRY_CNT 3 |
| |
| /* |
| * since the code already has built-in support for binning of up to MAX_FAULTY_TPCS TPCs |
| * and the code relies on that value (for array size etc..) we define another value |
| * for MAX faulty TPCs which reflects the cluster binning requirements |
| */ |
| #define MAX_CLUSTER_BINNING_FAULTY_TPCS 1 |
| #define MAX_FAULTY_XBARS 1 |
| #define MAX_FAULTY_EDMAS 1 |
| #define MAX_FAULTY_DECODERS 1 |
| |
| #define GAUDI2_TPC_FULL_MASK 0x1FFFFFF |
| #define GAUDI2_HIF_HMMU_FULL_MASK 0xFFFF |
| #define GAUDI2_DECODER_FULL_MASK 0x3FF |
| |
| #define GAUDI2_NA_EVENT_CAUSE 0xFF |
| #define GAUDI2_NUM_OF_QM_ERR_CAUSE 18 |
| #define GAUDI2_NUM_OF_LOWER_QM_ERR_CAUSE 25 |
| #define GAUDI2_NUM_OF_QM_ARB_ERR_CAUSE 3 |
| #define GAUDI2_NUM_OF_ARC_SEI_ERR_CAUSE 14 |
| #define GAUDI2_NUM_OF_CPU_SEI_ERR_CAUSE 3 |
| #define GAUDI2_NUM_OF_QM_SEI_ERR_CAUSE 2 |
| #define GAUDI2_NUM_OF_ROT_ERR_CAUSE 22 |
| #define GAUDI2_NUM_OF_TPC_INTR_CAUSE 31 |
| #define GAUDI2_NUM_OF_DEC_ERR_CAUSE 25 |
| #define GAUDI2_NUM_OF_MME_ERR_CAUSE 16 |
| #define GAUDI2_NUM_OF_MME_WAP_ERR_CAUSE 7 |
| #define GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE 8 |
| #define GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE 19 |
| #define GAUDI2_NUM_OF_HBM_SEI_CAUSE 9 |
| #define GAUDI2_NUM_OF_SM_SEI_ERR_CAUSE 3 |
| #define GAUDI2_NUM_OF_PCIE_ADDR_DEC_ERR_CAUSE 3 |
| #define GAUDI2_NUM_OF_PMMU_FATAL_ERR_CAUSE 2 |
| #define GAUDI2_NUM_OF_HIF_FATAL_ERR_CAUSE 2 |
| #define GAUDI2_NUM_OF_AXI_DRAIN_ERR_CAUSE 2 |
| #define GAUDI2_NUM_OF_HBM_MC_SPI_CAUSE 5 |
| |
| #define GAUDI2_MMU_CACHE_INV_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 10) |
| #define GAUDI2_PLDM_MMU_TIMEOUT_USEC (MMU_CONFIG_TIMEOUT_USEC * 200) |
| #define GAUDI2_ARB_WDT_TIMEOUT (0x1000000) |
| |
| #define GAUDI2_VDEC_TIMEOUT_USEC 10000 /* 10ms */ |
| #define GAUDI2_PLDM_VDEC_TIMEOUT_USEC (GAUDI2_VDEC_TIMEOUT_USEC * 100) |
| |
| #define KDMA_TIMEOUT_USEC USEC_PER_SEC |
| |
| #define IS_DMA_IDLE(dma_core_sts0) \ |
| (!((dma_core_sts0) & (DCORE0_EDMA0_CORE_STS0_BUSY_MASK))) |
| |
| #define IS_DMA_HALTED(dma_core_sts1) \ |
| ((dma_core_sts1) & (DCORE0_EDMA0_CORE_STS1_IS_HALT_MASK)) |
| |
| #define IS_MME_IDLE(mme_arch_sts) (((mme_arch_sts) & MME_ARCH_IDLE_MASK) == MME_ARCH_IDLE_MASK) |
| |
| #define IS_TPC_IDLE(tpc_cfg_sts) (((tpc_cfg_sts) & (TPC_IDLE_MASK)) == (TPC_IDLE_MASK)) |
| |
| #define IS_QM_IDLE(qm_glbl_sts0, qm_glbl_sts1, qm_cgm_sts) \ |
| ((((qm_glbl_sts0) & (QM_IDLE_MASK)) == (QM_IDLE_MASK)) && \ |
| (((qm_glbl_sts1) & (QM_ARC_IDLE_MASK)) == (QM_ARC_IDLE_MASK)) && \ |
| (((qm_cgm_sts) & (CGM_IDLE_MASK)) == (CGM_IDLE_MASK))) |
| |
| #define PCIE_DEC_EN_MASK 0x300 |
| #define DEC_WORK_STATE_IDLE 0 |
| #define DEC_WORK_STATE_PEND 3 |
| #define IS_DEC_IDLE(dec_swreg15) \ |
| (((dec_swreg15) & DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK) == DEC_WORK_STATE_IDLE || \ |
| ((dec_swreg15) & DCORE0_DEC0_CMD_SWREG15_SW_WORK_STATE_MASK) == DEC_WORK_STATE_PEND) |
| |
| /* HBM MMU address scrambling parameters */ |
| #define GAUDI2_HBM_MMU_SCRM_MEM_SIZE SZ_8M |
| #define GAUDI2_HBM_MMU_SCRM_DIV_SHIFT 26 |
| #define GAUDI2_HBM_MMU_SCRM_MOD_SHIFT 0 |
| #define GAUDI2_HBM_MMU_SCRM_ADDRESS_MASK DRAM_VA_HINT_MASK |
| #define GAUDI2_COMPENSATE_TLB_PAGE_SIZE_FACTOR 16 |
| #define MMU_RANGE_INV_VA_LSB_SHIFT 12 |
| #define MMU_RANGE_INV_VA_MSB_SHIFT 44 |
| #define MMU_RANGE_INV_EN_SHIFT 0 |
| #define MMU_RANGE_INV_ASID_EN_SHIFT 1 |
| #define MMU_RANGE_INV_ASID_SHIFT 2 |
| |
| /* The last SPI_SEI cause bit, "burst_fifo_full", is expected to be triggered in PMMU because it has |
| * a 2 entries FIFO, and hence it is not enabled for it. |
| */ |
| #define GAUDI2_PMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 2, 0) |
| #define GAUDI2_HMMU_SPI_SEI_ENABLE_MASK GENMASK(GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE - 1, 0) |
| |
| #define GAUDI2_MAX_STRING_LEN 64 |
| |
| #define GAUDI2_VDEC_MSIX_ENTRIES (GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM - \ |
| GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM + 1) |
| |
| #define ENGINE_ID_DCORE_OFFSET (GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0) |
| |
| /* RAZWI initiator coordinates */ |
| #define RAZWI_GET_AXUSER_XY(x) \ |
| ((x & 0xF8001FF0) >> 4) |
| |
| #define RAZWI_GET_AXUSER_LOW_XY(x) \ |
| ((x & 0x00001FF0) >> 4) |
| |
| #define RAZWI_INITIATOR_AXUER_L_X_SHIFT 0 |
| #define RAZWI_INITIATOR_AXUER_L_X_MASK 0x1F |
| #define RAZWI_INITIATOR_AXUER_L_Y_SHIFT 5 |
| #define RAZWI_INITIATOR_AXUER_L_Y_MASK 0xF |
| |
| #define RAZWI_INITIATOR_AXUER_H_X_SHIFT 23 |
| #define RAZWI_INITIATOR_AXUER_H_X_MASK 0x1F |
| |
| #define RAZWI_INITIATOR_ID_X_Y_LOW(x, y) \ |
| ((((y) & RAZWI_INITIATOR_AXUER_L_Y_MASK) << RAZWI_INITIATOR_AXUER_L_Y_SHIFT) | \ |
| (((x) & RAZWI_INITIATOR_AXUER_L_X_MASK) << RAZWI_INITIATOR_AXUER_L_X_SHIFT)) |
| |
| #define RAZWI_INITIATOR_ID_X_HIGH(x) \ |
| (((x) & RAZWI_INITIATOR_AXUER_H_X_MASK) << RAZWI_INITIATOR_AXUER_H_X_SHIFT) |
| |
| #define RAZWI_INITIATOR_ID_X_Y(xl, yl, xh) \ |
| (RAZWI_INITIATOR_ID_X_Y_LOW(xl, yl) | RAZWI_INITIATOR_ID_X_HIGH(xh)) |
| |
| #define PSOC_RAZWI_ENG_STR_SIZE 128 |
| #define PSOC_RAZWI_MAX_ENG_PER_RTR 5 |
| |
| /* HW scrambles only bits 0-25 */ |
| #define HW_UNSCRAMBLED_BITS_MASK GENMASK_ULL(63, 26) |
| |
| #define GAUDI2_GLBL_ERR_MAX_CAUSE_NUM 17 |
| |
| struct gaudi2_razwi_info { |
| u32 axuser_xy; |
| u32 rtr_ctrl; |
| u16 eng_id; |
| char *eng_name; |
| }; |
| |
| static struct gaudi2_razwi_info common_razwi_info[] = { |
| {RAZWI_INITIATOR_ID_X_Y(2, 4, 0), mmDCORE0_RTR0_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_DEC_0, "DEC0"}, |
| {RAZWI_INITIATOR_ID_X_Y(2, 4, 4), mmDCORE0_RTR0_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_DEC_1, "DEC1"}, |
| {RAZWI_INITIATOR_ID_X_Y(17, 4, 18), mmDCORE1_RTR7_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_DEC_0, "DEC2"}, |
| {RAZWI_INITIATOR_ID_X_Y(17, 4, 14), mmDCORE1_RTR7_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_DEC_1, "DEC3"}, |
| {RAZWI_INITIATOR_ID_X_Y(2, 11, 0), mmDCORE2_RTR0_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_DEC_0, "DEC4"}, |
| {RAZWI_INITIATOR_ID_X_Y(2, 11, 4), mmDCORE2_RTR0_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_DEC_1, "DEC5"}, |
| {RAZWI_INITIATOR_ID_X_Y(17, 11, 18), mmDCORE3_RTR7_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_DEC_0, "DEC6"}, |
| {RAZWI_INITIATOR_ID_X_Y(17, 11, 14), mmDCORE3_RTR7_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_DEC_1, "DEC7"}, |
| {RAZWI_INITIATOR_ID_X_Y(2, 4, 6), mmDCORE0_RTR0_CTRL_BASE, |
| GAUDI2_PCIE_ENGINE_ID_DEC_0, "DEC8"}, |
| {RAZWI_INITIATOR_ID_X_Y(2, 4, 7), mmDCORE0_RTR0_CTRL_BASE, |
| GAUDI2_PCIE_ENGINE_ID_DEC_0, "DEC9"}, |
| {RAZWI_INITIATOR_ID_X_Y(3, 4, 2), mmDCORE0_RTR1_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_TPC_0, "TPC0"}, |
| {RAZWI_INITIATOR_ID_X_Y(3, 4, 4), mmDCORE0_RTR1_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_TPC_1, "TPC1"}, |
| {RAZWI_INITIATOR_ID_X_Y(4, 4, 2), mmDCORE0_RTR2_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_TPC_2, "TPC2"}, |
| {RAZWI_INITIATOR_ID_X_Y(4, 4, 4), mmDCORE0_RTR2_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_TPC_3, "TPC3"}, |
| {RAZWI_INITIATOR_ID_X_Y(5, 4, 2), mmDCORE0_RTR3_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_TPC_4, "TPC4"}, |
| {RAZWI_INITIATOR_ID_X_Y(5, 4, 4), mmDCORE0_RTR3_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_TPC_5, "TPC5"}, |
| {RAZWI_INITIATOR_ID_X_Y(16, 4, 14), mmDCORE1_RTR6_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_TPC_0, "TPC6"}, |
| {RAZWI_INITIATOR_ID_X_Y(16, 4, 16), mmDCORE1_RTR6_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_TPC_1, "TPC7"}, |
| {RAZWI_INITIATOR_ID_X_Y(15, 4, 14), mmDCORE1_RTR5_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_TPC_2, "TPC8"}, |
| {RAZWI_INITIATOR_ID_X_Y(15, 4, 16), mmDCORE1_RTR5_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_TPC_3, "TPC9"}, |
| {RAZWI_INITIATOR_ID_X_Y(14, 4, 14), mmDCORE1_RTR4_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_TPC_4, "TPC10"}, |
| {RAZWI_INITIATOR_ID_X_Y(14, 4, 16), mmDCORE1_RTR4_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_TPC_5, "TPC11"}, |
| {RAZWI_INITIATOR_ID_X_Y(5, 11, 2), mmDCORE2_RTR3_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_TPC_0, "TPC12"}, |
| {RAZWI_INITIATOR_ID_X_Y(5, 11, 4), mmDCORE2_RTR3_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_TPC_1, "TPC13"}, |
| {RAZWI_INITIATOR_ID_X_Y(4, 11, 2), mmDCORE2_RTR2_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_TPC_2, "TPC14"}, |
| {RAZWI_INITIATOR_ID_X_Y(4, 11, 4), mmDCORE2_RTR2_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_TPC_3, "TPC15"}, |
| {RAZWI_INITIATOR_ID_X_Y(3, 11, 2), mmDCORE2_RTR1_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_TPC_4, "TPC16"}, |
| {RAZWI_INITIATOR_ID_X_Y(3, 11, 4), mmDCORE2_RTR1_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_TPC_5, "TPC17"}, |
| {RAZWI_INITIATOR_ID_X_Y(14, 11, 14), mmDCORE3_RTR4_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_TPC_0, "TPC18"}, |
| {RAZWI_INITIATOR_ID_X_Y(14, 11, 16), mmDCORE3_RTR4_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_TPC_1, "TPC19"}, |
| {RAZWI_INITIATOR_ID_X_Y(15, 11, 14), mmDCORE3_RTR5_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_TPC_2, "TPC20"}, |
| {RAZWI_INITIATOR_ID_X_Y(15, 11, 16), mmDCORE3_RTR5_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_TPC_3, "TPC21"}, |
| {RAZWI_INITIATOR_ID_X_Y(16, 11, 14), mmDCORE3_RTR6_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_TPC_4, "TPC22"}, |
| {RAZWI_INITIATOR_ID_X_Y(16, 11, 16), mmDCORE3_RTR6_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_TPC_5, "TPC23"}, |
| {RAZWI_INITIATOR_ID_X_Y(2, 4, 2), mmDCORE0_RTR0_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_TPC_5, "TPC24"}, |
| {RAZWI_INITIATOR_ID_X_Y(17, 4, 8), mmDCORE1_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_NIC0_0, "NIC0"}, |
| {RAZWI_INITIATOR_ID_X_Y(17, 4, 10), mmDCORE1_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_NIC0_1, "NIC1"}, |
| {RAZWI_INITIATOR_ID_X_Y(17, 4, 12), mmDCORE1_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_NIC1_0, "NIC2"}, |
| {RAZWI_INITIATOR_ID_X_Y(17, 4, 14), mmDCORE1_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_NIC1_1, "NIC3"}, |
| {RAZWI_INITIATOR_ID_X_Y(17, 4, 15), mmDCORE1_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_NIC2_0, "NIC4"}, |
| {RAZWI_INITIATOR_ID_X_Y(2, 11, 2), mmDCORE2_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_NIC2_1, "NIC5"}, |
| {RAZWI_INITIATOR_ID_X_Y(2, 11, 4), mmDCORE2_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_NIC3_0, "NIC6"}, |
| {RAZWI_INITIATOR_ID_X_Y(2, 11, 6), mmDCORE2_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_NIC3_1, "NIC7"}, |
| {RAZWI_INITIATOR_ID_X_Y(2, 11, 8), mmDCORE2_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_NIC4_0, "NIC8"}, |
| {RAZWI_INITIATOR_ID_X_Y(17, 11, 12), mmDCORE3_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_NIC4_1, "NIC9"}, |
| {RAZWI_INITIATOR_ID_X_Y(17, 11, 14), mmDCORE3_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_NIC5_0, "NIC10"}, |
| {RAZWI_INITIATOR_ID_X_Y(17, 11, 16), mmDCORE3_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_NIC5_1, "NIC11"}, |
| {RAZWI_INITIATOR_ID_X_Y(2, 4, 2), mmDCORE0_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_PDMA_0, "PDMA0"}, |
| {RAZWI_INITIATOR_ID_X_Y(2, 4, 3), mmDCORE0_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_PDMA_1, "PDMA1"}, |
| {RAZWI_INITIATOR_ID_X_Y(2, 4, 4), mmDCORE0_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "PMMU"}, |
| {RAZWI_INITIATOR_ID_X_Y(2, 4, 5), mmDCORE0_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "PCIE"}, |
| {RAZWI_INITIATOR_ID_X_Y(17, 4, 16), mmDCORE1_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_ARC_FARM, "ARC_FARM"}, |
| {RAZWI_INITIATOR_ID_X_Y(17, 4, 17), mmDCORE1_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_KDMA, "KDMA"}, |
| {RAZWI_INITIATOR_ID_X_Y(1, 5, 1), mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_EDMA_0, "EDMA0"}, |
| {RAZWI_INITIATOR_ID_X_Y(1, 5, 1), mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_EDMA_1, "EDMA1"}, |
| {RAZWI_INITIATOR_ID_X_Y(18, 5, 18), mmSFT1_HBW_RTR_IF1_RTR_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_EDMA_0, "EDMA2"}, |
| {RAZWI_INITIATOR_ID_X_Y(18, 5, 18), mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_EDMA_1, "EDMA3"}, |
| {RAZWI_INITIATOR_ID_X_Y(1, 10, 1), mmSFT2_HBW_RTR_IF0_RTR_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_EDMA_0, "EDMA4"}, |
| {RAZWI_INITIATOR_ID_X_Y(1, 10, 1), mmSFT2_HBW_RTR_IF1_RTR_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_EDMA_1, "EDMA5"}, |
| {RAZWI_INITIATOR_ID_X_Y(18, 10, 18), mmSFT2_HBW_RTR_IF0_RTR_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_EDMA_0, "EDMA6"}, |
| {RAZWI_INITIATOR_ID_X_Y(18, 10, 18), mmSFT2_HBW_RTR_IF1_RTR_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_EDMA_1, "EDMA7"}, |
| {RAZWI_INITIATOR_ID_X_Y(1, 5, 0), mmDCORE0_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "HMMU0"}, |
| {RAZWI_INITIATOR_ID_X_Y(18, 5, 19), mmDCORE1_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "HMMU1"}, |
| {RAZWI_INITIATOR_ID_X_Y(1, 5, 0), mmDCORE0_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "HMMU2"}, |
| {RAZWI_INITIATOR_ID_X_Y(18, 5, 19), mmDCORE1_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "HMMU3"}, |
| {RAZWI_INITIATOR_ID_X_Y(1, 5, 0), mmDCORE0_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "HMMU4"}, |
| {RAZWI_INITIATOR_ID_X_Y(18, 5, 19), mmDCORE1_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "HMMU5"}, |
| {RAZWI_INITIATOR_ID_X_Y(1, 5, 0), mmDCORE0_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "HMMU6"}, |
| {RAZWI_INITIATOR_ID_X_Y(18, 5, 19), mmDCORE1_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "HMMU7"}, |
| {RAZWI_INITIATOR_ID_X_Y(1, 10, 0), mmDCORE2_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "HMMU8"}, |
| {RAZWI_INITIATOR_ID_X_Y(18, 10, 19), mmDCORE3_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "HMMU9"}, |
| {RAZWI_INITIATOR_ID_X_Y(1, 10, 0), mmDCORE2_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "HMMU10"}, |
| {RAZWI_INITIATOR_ID_X_Y(18, 10, 19), mmDCORE3_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "HMMU11"}, |
| {RAZWI_INITIATOR_ID_X_Y(1, 10, 0), mmDCORE2_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "HMMU12"}, |
| {RAZWI_INITIATOR_ID_X_Y(18, 10, 19), mmDCORE3_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "HMMU13"}, |
| {RAZWI_INITIATOR_ID_X_Y(1, 10, 0), mmDCORE2_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "HMMU14"}, |
| {RAZWI_INITIATOR_ID_X_Y(18, 10, 19), mmDCORE3_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_SIZE, "HMMU15"}, |
| {RAZWI_INITIATOR_ID_X_Y(2, 11, 2), mmDCORE2_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_ROT_0, "ROT0"}, |
| {RAZWI_INITIATOR_ID_X_Y(17, 11, 16), mmDCORE3_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_ROT_1, "ROT1"}, |
| {RAZWI_INITIATOR_ID_X_Y(2, 11, 2), mmDCORE2_RTR0_CTRL_BASE, |
| GAUDI2_ENGINE_ID_PSOC, "CPU"}, |
| {RAZWI_INITIATOR_ID_X_Y(17, 11, 11), mmDCORE3_RTR7_CTRL_BASE, |
| GAUDI2_ENGINE_ID_PSOC, "PSOC"} |
| }; |
| |
| static struct gaudi2_razwi_info mme_razwi_info[] = { |
| /* MME X high coordinate is N/A, hence using only low coordinates */ |
| {RAZWI_INITIATOR_ID_X_Y_LOW(7, 4), mmDCORE0_RTR5_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_WAP0"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(9, 4), mmDCORE0_RTR7_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_WAP1"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(8, 4), mmDCORE0_RTR6_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_CTRL_WR"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(9, 4), mmDCORE0_RTR7_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_CTRL_RD"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(6, 4), mmDCORE0_RTR4_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE0"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(6, 4), mmDCORE0_RTR4_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE1"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(7, 4), mmDCORE0_RTR5_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE2"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(8, 4), mmDCORE0_RTR6_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE3"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(9, 4), mmDCORE0_RTR7_CTRL_BASE, |
| GAUDI2_DCORE0_ENGINE_ID_MME, "MME0_SBTE4"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(12, 4), mmDCORE1_RTR2_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_WAP0"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(10, 4), mmDCORE1_RTR0_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_WAP1"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(11, 4), mmDCORE1_RTR1_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_CTRL_WR"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(10, 4), mmDCORE1_RTR0_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_CTRL_RD"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(13, 4), mmDCORE1_RTR3_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE0"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(13, 4), mmDCORE1_RTR3_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE1"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(12, 4), mmDCORE1_RTR2_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE2"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(11, 4), mmDCORE1_RTR1_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE3"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(10, 4), mmDCORE1_RTR0_CTRL_BASE, |
| GAUDI2_DCORE1_ENGINE_ID_MME, "MME1_SBTE4"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(7, 11), mmDCORE2_RTR5_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_WAP0"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(9, 11), mmDCORE2_RTR7_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_WAP1"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(8, 11), mmDCORE2_RTR6_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_CTRL_WR"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(9, 11), mmDCORE2_RTR7_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_CTRL_RD"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(6, 11), mmDCORE2_RTR4_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE0"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(6, 11), mmDCORE2_RTR4_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE1"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(7, 11), mmDCORE2_RTR5_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE2"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(8, 11), mmDCORE2_RTR6_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE3"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(9, 11), mmDCORE2_RTR7_CTRL_BASE, |
| GAUDI2_DCORE2_ENGINE_ID_MME, "MME2_SBTE4"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(12, 11), mmDCORE3_RTR2_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_WAP0"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(10, 11), mmDCORE3_RTR0_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_WAP1"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(11, 11), mmDCORE3_RTR1_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_CTRL_WR"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(10, 11), mmDCORE3_RTR0_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_CTRL_RD"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(13, 11), mmDCORE3_RTR3_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE0"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(13, 11), mmDCORE3_RTR3_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE1"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(12, 11), mmDCORE3_RTR2_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE2"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(11, 11), mmDCORE3_RTR1_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE3"}, |
| {RAZWI_INITIATOR_ID_X_Y_LOW(10, 11), mmDCORE3_RTR0_CTRL_BASE, |
| GAUDI2_DCORE3_ENGINE_ID_MME, "MME3_SBTE4"} |
| }; |
| |
| enum hl_pmmu_fatal_cause { |
| LATENCY_RD_OUT_FIFO_OVERRUN, |
| LATENCY_WR_OUT_FIFO_OVERRUN, |
| }; |
| |
| enum hl_pcie_drain_ind_cause { |
| LBW_AXI_DRAIN_IND, |
| HBW_AXI_DRAIN_IND |
| }; |
| |
| static const u32 cluster_hmmu_hif_enabled_mask[GAUDI2_HBM_NUM] = { |
| [HBM_ID0] = 0xFFFC, |
| [HBM_ID1] = 0xFFCF, |
| [HBM_ID2] = 0xF7F7, |
| [HBM_ID3] = 0x7F7F, |
| [HBM_ID4] = 0xFCFF, |
| [HBM_ID5] = 0xCFFF, |
| }; |
| |
| static const u8 xbar_edge_to_hbm_cluster[EDMA_ID_SIZE] = { |
| [0] = HBM_ID0, |
| [1] = HBM_ID1, |
| [2] = HBM_ID4, |
| [3] = HBM_ID5, |
| }; |
| |
| static const u8 edma_to_hbm_cluster[EDMA_ID_SIZE] = { |
| [EDMA_ID_DCORE0_INSTANCE0] = HBM_ID0, |
| [EDMA_ID_DCORE0_INSTANCE1] = HBM_ID2, |
| [EDMA_ID_DCORE1_INSTANCE0] = HBM_ID1, |
| [EDMA_ID_DCORE1_INSTANCE1] = HBM_ID3, |
| [EDMA_ID_DCORE2_INSTANCE0] = HBM_ID2, |
| [EDMA_ID_DCORE2_INSTANCE1] = HBM_ID4, |
| [EDMA_ID_DCORE3_INSTANCE0] = HBM_ID3, |
| [EDMA_ID_DCORE3_INSTANCE1] = HBM_ID5, |
| }; |
| |
| static const int gaudi2_qman_async_event_id[] = { |
| [GAUDI2_QUEUE_ID_PDMA_0_0] = GAUDI2_EVENT_PDMA0_QM, |
| [GAUDI2_QUEUE_ID_PDMA_0_1] = GAUDI2_EVENT_PDMA0_QM, |
| [GAUDI2_QUEUE_ID_PDMA_0_2] = GAUDI2_EVENT_PDMA0_QM, |
| [GAUDI2_QUEUE_ID_PDMA_0_3] = GAUDI2_EVENT_PDMA0_QM, |
| [GAUDI2_QUEUE_ID_PDMA_1_0] = GAUDI2_EVENT_PDMA1_QM, |
| [GAUDI2_QUEUE_ID_PDMA_1_1] = GAUDI2_EVENT_PDMA1_QM, |
| [GAUDI2_QUEUE_ID_PDMA_1_2] = GAUDI2_EVENT_PDMA1_QM, |
| [GAUDI2_QUEUE_ID_PDMA_1_3] = GAUDI2_EVENT_PDMA1_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0] = GAUDI2_EVENT_HDMA0_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1] = GAUDI2_EVENT_HDMA0_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2] = GAUDI2_EVENT_HDMA0_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3] = GAUDI2_EVENT_HDMA0_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0] = GAUDI2_EVENT_HDMA1_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1] = GAUDI2_EVENT_HDMA1_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2] = GAUDI2_EVENT_HDMA1_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3] = GAUDI2_EVENT_HDMA1_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_MME_0_0] = GAUDI2_EVENT_MME0_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_MME_0_1] = GAUDI2_EVENT_MME0_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_MME_0_2] = GAUDI2_EVENT_MME0_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_MME_0_3] = GAUDI2_EVENT_MME0_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_0_0] = GAUDI2_EVENT_TPC0_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_0_1] = GAUDI2_EVENT_TPC0_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_0_2] = GAUDI2_EVENT_TPC0_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_0_3] = GAUDI2_EVENT_TPC0_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_1_0] = GAUDI2_EVENT_TPC1_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_1_1] = GAUDI2_EVENT_TPC1_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_1_2] = GAUDI2_EVENT_TPC1_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_1_3] = GAUDI2_EVENT_TPC1_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_2_0] = GAUDI2_EVENT_TPC2_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_2_1] = GAUDI2_EVENT_TPC2_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_2_2] = GAUDI2_EVENT_TPC2_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_2_3] = GAUDI2_EVENT_TPC2_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_3_0] = GAUDI2_EVENT_TPC3_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_3_1] = GAUDI2_EVENT_TPC3_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_3_2] = GAUDI2_EVENT_TPC3_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_3_3] = GAUDI2_EVENT_TPC3_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_4_0] = GAUDI2_EVENT_TPC4_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_4_1] = GAUDI2_EVENT_TPC4_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_4_2] = GAUDI2_EVENT_TPC4_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_4_3] = GAUDI2_EVENT_TPC4_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_5_0] = GAUDI2_EVENT_TPC5_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_5_1] = GAUDI2_EVENT_TPC5_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_5_2] = GAUDI2_EVENT_TPC5_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_5_3] = GAUDI2_EVENT_TPC5_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_6_0] = GAUDI2_EVENT_TPC24_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_6_1] = GAUDI2_EVENT_TPC24_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_6_2] = GAUDI2_EVENT_TPC24_QM, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_6_3] = GAUDI2_EVENT_TPC24_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0] = GAUDI2_EVENT_HDMA2_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1] = GAUDI2_EVENT_HDMA2_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2] = GAUDI2_EVENT_HDMA2_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3] = GAUDI2_EVENT_HDMA2_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0] = GAUDI2_EVENT_HDMA3_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1] = GAUDI2_EVENT_HDMA3_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2] = GAUDI2_EVENT_HDMA3_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3] = GAUDI2_EVENT_HDMA3_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_MME_0_0] = GAUDI2_EVENT_MME1_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_MME_0_1] = GAUDI2_EVENT_MME1_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_MME_0_2] = GAUDI2_EVENT_MME1_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_MME_0_3] = GAUDI2_EVENT_MME1_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_0_0] = GAUDI2_EVENT_TPC6_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_0_1] = GAUDI2_EVENT_TPC6_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_0_2] = GAUDI2_EVENT_TPC6_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_0_3] = GAUDI2_EVENT_TPC6_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_1_0] = GAUDI2_EVENT_TPC7_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_1_1] = GAUDI2_EVENT_TPC7_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_1_2] = GAUDI2_EVENT_TPC7_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_1_3] = GAUDI2_EVENT_TPC7_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_2_0] = GAUDI2_EVENT_TPC8_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_2_1] = GAUDI2_EVENT_TPC8_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_2_2] = GAUDI2_EVENT_TPC8_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_2_3] = GAUDI2_EVENT_TPC8_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_3_0] = GAUDI2_EVENT_TPC9_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_3_1] = GAUDI2_EVENT_TPC9_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_3_2] = GAUDI2_EVENT_TPC9_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_3_3] = GAUDI2_EVENT_TPC9_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_4_0] = GAUDI2_EVENT_TPC10_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_4_1] = GAUDI2_EVENT_TPC10_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_4_2] = GAUDI2_EVENT_TPC10_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_4_3] = GAUDI2_EVENT_TPC10_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_5_0] = GAUDI2_EVENT_TPC11_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_5_1] = GAUDI2_EVENT_TPC11_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_5_2] = GAUDI2_EVENT_TPC11_QM, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_5_3] = GAUDI2_EVENT_TPC11_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0] = GAUDI2_EVENT_HDMA4_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1] = GAUDI2_EVENT_HDMA4_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2] = GAUDI2_EVENT_HDMA4_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3] = GAUDI2_EVENT_HDMA4_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0] = GAUDI2_EVENT_HDMA5_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1] = GAUDI2_EVENT_HDMA5_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2] = GAUDI2_EVENT_HDMA5_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3] = GAUDI2_EVENT_HDMA5_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_MME_0_0] = GAUDI2_EVENT_MME2_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_MME_0_1] = GAUDI2_EVENT_MME2_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_MME_0_2] = GAUDI2_EVENT_MME2_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_MME_0_3] = GAUDI2_EVENT_MME2_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_0_0] = GAUDI2_EVENT_TPC12_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_0_1] = GAUDI2_EVENT_TPC12_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_0_2] = GAUDI2_EVENT_TPC12_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_0_3] = GAUDI2_EVENT_TPC12_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_1_0] = GAUDI2_EVENT_TPC13_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_1_1] = GAUDI2_EVENT_TPC13_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_1_2] = GAUDI2_EVENT_TPC13_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_1_3] = GAUDI2_EVENT_TPC13_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_2_0] = GAUDI2_EVENT_TPC14_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_2_1] = GAUDI2_EVENT_TPC14_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_2_2] = GAUDI2_EVENT_TPC14_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_2_3] = GAUDI2_EVENT_TPC14_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_3_0] = GAUDI2_EVENT_TPC15_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_3_1] = GAUDI2_EVENT_TPC15_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_3_2] = GAUDI2_EVENT_TPC15_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_3_3] = GAUDI2_EVENT_TPC15_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_4_0] = GAUDI2_EVENT_TPC16_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_4_1] = GAUDI2_EVENT_TPC16_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_4_2] = GAUDI2_EVENT_TPC16_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_4_3] = GAUDI2_EVENT_TPC16_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_5_0] = GAUDI2_EVENT_TPC17_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_5_1] = GAUDI2_EVENT_TPC17_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_5_2] = GAUDI2_EVENT_TPC17_QM, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_5_3] = GAUDI2_EVENT_TPC17_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0] = GAUDI2_EVENT_HDMA6_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1] = GAUDI2_EVENT_HDMA6_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2] = GAUDI2_EVENT_HDMA6_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3] = GAUDI2_EVENT_HDMA6_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0] = GAUDI2_EVENT_HDMA7_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1] = GAUDI2_EVENT_HDMA7_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2] = GAUDI2_EVENT_HDMA7_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3] = GAUDI2_EVENT_HDMA7_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_MME_0_0] = GAUDI2_EVENT_MME3_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_MME_0_1] = GAUDI2_EVENT_MME3_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_MME_0_2] = GAUDI2_EVENT_MME3_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_MME_0_3] = GAUDI2_EVENT_MME3_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_0_0] = GAUDI2_EVENT_TPC18_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_0_1] = GAUDI2_EVENT_TPC18_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_0_2] = GAUDI2_EVENT_TPC18_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_0_3] = GAUDI2_EVENT_TPC18_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_1_0] = GAUDI2_EVENT_TPC19_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_1_1] = GAUDI2_EVENT_TPC19_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_1_2] = GAUDI2_EVENT_TPC19_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_1_3] = GAUDI2_EVENT_TPC19_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_2_0] = GAUDI2_EVENT_TPC20_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_2_1] = GAUDI2_EVENT_TPC20_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_2_2] = GAUDI2_EVENT_TPC20_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_2_3] = GAUDI2_EVENT_TPC20_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_3_0] = GAUDI2_EVENT_TPC21_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_3_1] = GAUDI2_EVENT_TPC21_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_3_2] = GAUDI2_EVENT_TPC21_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_3_3] = GAUDI2_EVENT_TPC21_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_4_0] = GAUDI2_EVENT_TPC22_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_4_1] = GAUDI2_EVENT_TPC22_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_4_2] = GAUDI2_EVENT_TPC22_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_4_3] = GAUDI2_EVENT_TPC22_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_5_0] = GAUDI2_EVENT_TPC23_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_5_1] = GAUDI2_EVENT_TPC23_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_5_2] = GAUDI2_EVENT_TPC23_QM, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_5_3] = GAUDI2_EVENT_TPC23_QM, |
| [GAUDI2_QUEUE_ID_NIC_0_0] = GAUDI2_EVENT_NIC0_QM0, |
| [GAUDI2_QUEUE_ID_NIC_0_1] = GAUDI2_EVENT_NIC0_QM0, |
| [GAUDI2_QUEUE_ID_NIC_0_2] = GAUDI2_EVENT_NIC0_QM0, |
| [GAUDI2_QUEUE_ID_NIC_0_3] = GAUDI2_EVENT_NIC0_QM0, |
| [GAUDI2_QUEUE_ID_NIC_1_0] = GAUDI2_EVENT_NIC0_QM1, |
| [GAUDI2_QUEUE_ID_NIC_1_1] = GAUDI2_EVENT_NIC0_QM1, |
| [GAUDI2_QUEUE_ID_NIC_1_2] = GAUDI2_EVENT_NIC0_QM1, |
| [GAUDI2_QUEUE_ID_NIC_1_3] = GAUDI2_EVENT_NIC0_QM1, |
| [GAUDI2_QUEUE_ID_NIC_2_0] = GAUDI2_EVENT_NIC1_QM0, |
| [GAUDI2_QUEUE_ID_NIC_2_1] = GAUDI2_EVENT_NIC1_QM0, |
| [GAUDI2_QUEUE_ID_NIC_2_2] = GAUDI2_EVENT_NIC1_QM0, |
| [GAUDI2_QUEUE_ID_NIC_2_3] = GAUDI2_EVENT_NIC1_QM0, |
| [GAUDI2_QUEUE_ID_NIC_3_0] = GAUDI2_EVENT_NIC1_QM1, |
| [GAUDI2_QUEUE_ID_NIC_3_1] = GAUDI2_EVENT_NIC1_QM1, |
| [GAUDI2_QUEUE_ID_NIC_3_2] = GAUDI2_EVENT_NIC1_QM1, |
| [GAUDI2_QUEUE_ID_NIC_3_3] = GAUDI2_EVENT_NIC1_QM1, |
| [GAUDI2_QUEUE_ID_NIC_4_0] = GAUDI2_EVENT_NIC2_QM0, |
| [GAUDI2_QUEUE_ID_NIC_4_1] = GAUDI2_EVENT_NIC2_QM0, |
| [GAUDI2_QUEUE_ID_NIC_4_2] = GAUDI2_EVENT_NIC2_QM0, |
| [GAUDI2_QUEUE_ID_NIC_4_3] = GAUDI2_EVENT_NIC2_QM0, |
| [GAUDI2_QUEUE_ID_NIC_5_0] = GAUDI2_EVENT_NIC2_QM1, |
| [GAUDI2_QUEUE_ID_NIC_5_1] = GAUDI2_EVENT_NIC2_QM1, |
| [GAUDI2_QUEUE_ID_NIC_5_2] = GAUDI2_EVENT_NIC2_QM1, |
| [GAUDI2_QUEUE_ID_NIC_5_3] = GAUDI2_EVENT_NIC2_QM1, |
| [GAUDI2_QUEUE_ID_NIC_6_0] = GAUDI2_EVENT_NIC3_QM0, |
| [GAUDI2_QUEUE_ID_NIC_6_1] = GAUDI2_EVENT_NIC3_QM0, |
| [GAUDI2_QUEUE_ID_NIC_6_2] = GAUDI2_EVENT_NIC3_QM0, |
| [GAUDI2_QUEUE_ID_NIC_6_3] = GAUDI2_EVENT_NIC3_QM0, |
| [GAUDI2_QUEUE_ID_NIC_7_0] = GAUDI2_EVENT_NIC3_QM1, |
| [GAUDI2_QUEUE_ID_NIC_7_1] = GAUDI2_EVENT_NIC3_QM1, |
| [GAUDI2_QUEUE_ID_NIC_7_2] = GAUDI2_EVENT_NIC3_QM1, |
| [GAUDI2_QUEUE_ID_NIC_7_3] = GAUDI2_EVENT_NIC3_QM1, |
| [GAUDI2_QUEUE_ID_NIC_8_0] = GAUDI2_EVENT_NIC4_QM0, |
| [GAUDI2_QUEUE_ID_NIC_8_1] = GAUDI2_EVENT_NIC4_QM0, |
| [GAUDI2_QUEUE_ID_NIC_8_2] = GAUDI2_EVENT_NIC4_QM0, |
| [GAUDI2_QUEUE_ID_NIC_8_3] = GAUDI2_EVENT_NIC4_QM0, |
| [GAUDI2_QUEUE_ID_NIC_9_0] = GAUDI2_EVENT_NIC4_QM1, |
| [GAUDI2_QUEUE_ID_NIC_9_1] = GAUDI2_EVENT_NIC4_QM1, |
| [GAUDI2_QUEUE_ID_NIC_9_2] = GAUDI2_EVENT_NIC4_QM1, |
| [GAUDI2_QUEUE_ID_NIC_9_3] = GAUDI2_EVENT_NIC4_QM1, |
| [GAUDI2_QUEUE_ID_NIC_10_0] = GAUDI2_EVENT_NIC5_QM0, |
| [GAUDI2_QUEUE_ID_NIC_10_1] = GAUDI2_EVENT_NIC5_QM0, |
| [GAUDI2_QUEUE_ID_NIC_10_2] = GAUDI2_EVENT_NIC5_QM0, |
| [GAUDI2_QUEUE_ID_NIC_10_3] = GAUDI2_EVENT_NIC5_QM0, |
| [GAUDI2_QUEUE_ID_NIC_11_0] = GAUDI2_EVENT_NIC5_QM1, |
| [GAUDI2_QUEUE_ID_NIC_11_1] = GAUDI2_EVENT_NIC5_QM1, |
| [GAUDI2_QUEUE_ID_NIC_11_2] = GAUDI2_EVENT_NIC5_QM1, |
| [GAUDI2_QUEUE_ID_NIC_11_3] = GAUDI2_EVENT_NIC5_QM1, |
| [GAUDI2_QUEUE_ID_NIC_12_0] = GAUDI2_EVENT_NIC6_QM0, |
| [GAUDI2_QUEUE_ID_NIC_12_1] = GAUDI2_EVENT_NIC6_QM0, |
| [GAUDI2_QUEUE_ID_NIC_12_2] = GAUDI2_EVENT_NIC6_QM0, |
| [GAUDI2_QUEUE_ID_NIC_12_3] = GAUDI2_EVENT_NIC6_QM0, |
| [GAUDI2_QUEUE_ID_NIC_13_0] = GAUDI2_EVENT_NIC6_QM1, |
| [GAUDI2_QUEUE_ID_NIC_13_1] = GAUDI2_EVENT_NIC6_QM1, |
| [GAUDI2_QUEUE_ID_NIC_13_2] = GAUDI2_EVENT_NIC6_QM1, |
| [GAUDI2_QUEUE_ID_NIC_13_3] = GAUDI2_EVENT_NIC6_QM1, |
| [GAUDI2_QUEUE_ID_NIC_14_0] = GAUDI2_EVENT_NIC7_QM0, |
| [GAUDI2_QUEUE_ID_NIC_14_1] = GAUDI2_EVENT_NIC7_QM0, |
| [GAUDI2_QUEUE_ID_NIC_14_2] = GAUDI2_EVENT_NIC7_QM0, |
| [GAUDI2_QUEUE_ID_NIC_14_3] = GAUDI2_EVENT_NIC7_QM0, |
| [GAUDI2_QUEUE_ID_NIC_15_0] = GAUDI2_EVENT_NIC7_QM1, |
| [GAUDI2_QUEUE_ID_NIC_15_1] = GAUDI2_EVENT_NIC7_QM1, |
| [GAUDI2_QUEUE_ID_NIC_15_2] = GAUDI2_EVENT_NIC7_QM1, |
| [GAUDI2_QUEUE_ID_NIC_15_3] = GAUDI2_EVENT_NIC7_QM1, |
| [GAUDI2_QUEUE_ID_NIC_16_0] = GAUDI2_EVENT_NIC8_QM0, |
| [GAUDI2_QUEUE_ID_NIC_16_1] = GAUDI2_EVENT_NIC8_QM0, |
| [GAUDI2_QUEUE_ID_NIC_16_2] = GAUDI2_EVENT_NIC8_QM0, |
| [GAUDI2_QUEUE_ID_NIC_16_3] = GAUDI2_EVENT_NIC8_QM0, |
| [GAUDI2_QUEUE_ID_NIC_17_0] = GAUDI2_EVENT_NIC8_QM1, |
| [GAUDI2_QUEUE_ID_NIC_17_1] = GAUDI2_EVENT_NIC8_QM1, |
| [GAUDI2_QUEUE_ID_NIC_17_2] = GAUDI2_EVENT_NIC8_QM1, |
| [GAUDI2_QUEUE_ID_NIC_17_3] = GAUDI2_EVENT_NIC8_QM1, |
| [GAUDI2_QUEUE_ID_NIC_18_0] = GAUDI2_EVENT_NIC9_QM0, |
| [GAUDI2_QUEUE_ID_NIC_18_1] = GAUDI2_EVENT_NIC9_QM0, |
| [GAUDI2_QUEUE_ID_NIC_18_2] = GAUDI2_EVENT_NIC9_QM0, |
| [GAUDI2_QUEUE_ID_NIC_18_3] = GAUDI2_EVENT_NIC9_QM0, |
| [GAUDI2_QUEUE_ID_NIC_19_0] = GAUDI2_EVENT_NIC9_QM1, |
| [GAUDI2_QUEUE_ID_NIC_19_1] = GAUDI2_EVENT_NIC9_QM1, |
| [GAUDI2_QUEUE_ID_NIC_19_2] = GAUDI2_EVENT_NIC9_QM1, |
| [GAUDI2_QUEUE_ID_NIC_19_3] = GAUDI2_EVENT_NIC9_QM1, |
| [GAUDI2_QUEUE_ID_NIC_20_0] = GAUDI2_EVENT_NIC10_QM0, |
| [GAUDI2_QUEUE_ID_NIC_20_1] = GAUDI2_EVENT_NIC10_QM0, |
| [GAUDI2_QUEUE_ID_NIC_20_2] = GAUDI2_EVENT_NIC10_QM0, |
| [GAUDI2_QUEUE_ID_NIC_20_3] = GAUDI2_EVENT_NIC10_QM0, |
| [GAUDI2_QUEUE_ID_NIC_21_0] = GAUDI2_EVENT_NIC10_QM1, |
| [GAUDI2_QUEUE_ID_NIC_21_1] = GAUDI2_EVENT_NIC10_QM1, |
| [GAUDI2_QUEUE_ID_NIC_21_2] = GAUDI2_EVENT_NIC10_QM1, |
| [GAUDI2_QUEUE_ID_NIC_21_3] = GAUDI2_EVENT_NIC10_QM1, |
| [GAUDI2_QUEUE_ID_NIC_22_0] = GAUDI2_EVENT_NIC11_QM0, |
| [GAUDI2_QUEUE_ID_NIC_22_1] = GAUDI2_EVENT_NIC11_QM0, |
| [GAUDI2_QUEUE_ID_NIC_22_2] = GAUDI2_EVENT_NIC11_QM0, |
| [GAUDI2_QUEUE_ID_NIC_22_3] = GAUDI2_EVENT_NIC11_QM0, |
| [GAUDI2_QUEUE_ID_NIC_23_0] = GAUDI2_EVENT_NIC11_QM1, |
| [GAUDI2_QUEUE_ID_NIC_23_1] = GAUDI2_EVENT_NIC11_QM1, |
| [GAUDI2_QUEUE_ID_NIC_23_2] = GAUDI2_EVENT_NIC11_QM1, |
| [GAUDI2_QUEUE_ID_NIC_23_3] = GAUDI2_EVENT_NIC11_QM1, |
| [GAUDI2_QUEUE_ID_ROT_0_0] = GAUDI2_EVENT_ROTATOR0_ROT0_QM, |
| [GAUDI2_QUEUE_ID_ROT_0_1] = GAUDI2_EVENT_ROTATOR0_ROT0_QM, |
| [GAUDI2_QUEUE_ID_ROT_0_2] = GAUDI2_EVENT_ROTATOR0_ROT0_QM, |
| [GAUDI2_QUEUE_ID_ROT_0_3] = GAUDI2_EVENT_ROTATOR0_ROT0_QM, |
| [GAUDI2_QUEUE_ID_ROT_1_0] = GAUDI2_EVENT_ROTATOR1_ROT1_QM, |
| [GAUDI2_QUEUE_ID_ROT_1_1] = GAUDI2_EVENT_ROTATOR1_ROT1_QM, |
| [GAUDI2_QUEUE_ID_ROT_1_2] = GAUDI2_EVENT_ROTATOR1_ROT1_QM, |
| [GAUDI2_QUEUE_ID_ROT_1_3] = GAUDI2_EVENT_ROTATOR1_ROT1_QM |
| }; |
| |
| static const int gaudi2_dma_core_async_event_id[] = { |
| [DMA_CORE_ID_EDMA0] = GAUDI2_EVENT_HDMA0_CORE, |
| [DMA_CORE_ID_EDMA1] = GAUDI2_EVENT_HDMA1_CORE, |
| [DMA_CORE_ID_EDMA2] = GAUDI2_EVENT_HDMA2_CORE, |
| [DMA_CORE_ID_EDMA3] = GAUDI2_EVENT_HDMA3_CORE, |
| [DMA_CORE_ID_EDMA4] = GAUDI2_EVENT_HDMA4_CORE, |
| [DMA_CORE_ID_EDMA5] = GAUDI2_EVENT_HDMA5_CORE, |
| [DMA_CORE_ID_EDMA6] = GAUDI2_EVENT_HDMA6_CORE, |
| [DMA_CORE_ID_EDMA7] = GAUDI2_EVENT_HDMA7_CORE, |
| [DMA_CORE_ID_PDMA0] = GAUDI2_EVENT_PDMA0_CORE, |
| [DMA_CORE_ID_PDMA1] = GAUDI2_EVENT_PDMA1_CORE, |
| [DMA_CORE_ID_KDMA] = GAUDI2_EVENT_KDMA0_CORE, |
| }; |
| |
| static const char * const gaudi2_qm_sei_error_cause[GAUDI2_NUM_OF_QM_SEI_ERR_CAUSE] = { |
| "qman sei intr", |
| "arc sei intr" |
| }; |
| |
| static const char * const gaudi2_cpu_sei_error_cause[GAUDI2_NUM_OF_CPU_SEI_ERR_CAUSE] = { |
| "AXI_TERMINATOR WR", |
| "AXI_TERMINATOR RD", |
| "AXI SPLIT SEI Status" |
| }; |
| |
| static const char * const gaudi2_arc_sei_error_cause[GAUDI2_NUM_OF_ARC_SEI_ERR_CAUSE] = { |
| "cbu_bresp_sei_intr_cause", |
| "cbu_rresp_sei_intr_cause", |
| "lbu_bresp_sei_intr_cause", |
| "lbu_rresp_sei_intr_cause", |
| "cbu_axi_split_intr_cause", |
| "lbu_axi_split_intr_cause", |
| "arc_ip_excptn_sei_intr_cause", |
| "dmi_bresp_sei_intr_cause", |
| "aux2apb_err_sei_intr_cause", |
| "cfg_lbw_wr_terminated_intr_cause", |
| "cfg_lbw_rd_terminated_intr_cause", |
| "cfg_dccm_wr_terminated_intr_cause", |
| "cfg_dccm_rd_terminated_intr_cause", |
| "cfg_hbw_rd_terminated_intr_cause" |
| }; |
| |
| static const char * const gaudi2_dec_error_cause[GAUDI2_NUM_OF_DEC_ERR_CAUSE] = { |
| "msix_vcd_hbw_sei", |
| "msix_l2c_hbw_sei", |
| "msix_nrm_hbw_sei", |
| "msix_abnrm_hbw_sei", |
| "msix_vcd_lbw_sei", |
| "msix_l2c_lbw_sei", |
| "msix_nrm_lbw_sei", |
| "msix_abnrm_lbw_sei", |
| "apb_vcd_lbw_sei", |
| "apb_l2c_lbw_sei", |
| "apb_nrm_lbw_sei", |
| "apb_abnrm_lbw_sei", |
| "dec_sei", |
| "dec_apb_sei", |
| "trc_apb_sei", |
| "lbw_mstr_if_sei", |
| "axi_split_bresp_err_sei", |
| "hbw_axi_wr_viol_sei", |
| "hbw_axi_rd_viol_sei", |
| "lbw_axi_wr_viol_sei", |
| "lbw_axi_rd_viol_sei", |
| "vcd_spi", |
| "l2c_spi", |
| "nrm_spi", |
| "abnrm_spi", |
| }; |
| |
| static const char * const gaudi2_qman_error_cause[GAUDI2_NUM_OF_QM_ERR_CAUSE] = { |
| "PQ AXI HBW error", |
| "CQ AXI HBW error", |
| "CP AXI HBW error", |
| "CP error due to undefined OPCODE", |
| "CP encountered STOP OPCODE", |
| "CP AXI LBW error", |
| "CP WRREG32 or WRBULK returned error", |
| "N/A", |
| "FENCE 0 inc over max value and clipped", |
| "FENCE 1 inc over max value and clipped", |
| "FENCE 2 inc over max value and clipped", |
| "FENCE 3 inc over max value and clipped", |
| "FENCE 0 dec under min value and clipped", |
| "FENCE 1 dec under min value and clipped", |
| "FENCE 2 dec under min value and clipped", |
| "FENCE 3 dec under min value and clipped", |
| "CPDMA Up overflow", |
| "PQC L2H error" |
| }; |
| |
| static const char * const gaudi2_lower_qman_error_cause[GAUDI2_NUM_OF_LOWER_QM_ERR_CAUSE] = { |
| "RSVD0", |
| "CQ AXI HBW error", |
| "CP AXI HBW error", |
| "CP error due to undefined OPCODE", |
| "CP encountered STOP OPCODE", |
| "CP AXI LBW error", |
| "CP WRREG32 or WRBULK returned error", |
| "N/A", |
| "FENCE 0 inc over max value and clipped", |
| "FENCE 1 inc over max value and clipped", |
| "FENCE 2 inc over max value and clipped", |
| "FENCE 3 inc over max value and clipped", |
| "FENCE 0 dec under min value and clipped", |
| "FENCE 1 dec under min value and clipped", |
| "FENCE 2 dec under min value and clipped", |
| "FENCE 3 dec under min value and clipped", |
| "CPDMA Up overflow", |
| "RSVD17", |
| "CQ_WR_IFIFO_CI_ERR", |
| "CQ_WR_CTL_CI_ERR", |
| "ARC_CQF_RD_ERR", |
| "ARC_CQ_WR_IFIFO_CI_ERR", |
| "ARC_CQ_WR_CTL_CI_ERR", |
| "ARC_AXI_ERR", |
| "CP_SWITCH_WDT_ERR" |
| }; |
| |
| static const char * const gaudi2_qman_arb_error_cause[GAUDI2_NUM_OF_QM_ARB_ERR_CAUSE] = { |
| "Choice push while full error", |
| "Choice Q watchdog error", |
| "MSG AXI LBW returned with error" |
| }; |
| |
| static const char * const guadi2_rot_error_cause[GAUDI2_NUM_OF_ROT_ERR_CAUSE] = { |
| "qm_axi_err", |
| "qm_trace_fence_events", |
| "qm_sw_err", |
| "qm_cp_sw_stop", |
| "lbw_mstr_rresp_err", |
| "lbw_mstr_bresp_err", |
| "lbw_msg_slverr", |
| "hbw_msg_slverr", |
| "wbc_slverr", |
| "hbw_mstr_rresp_err", |
| "hbw_mstr_bresp_err", |
| "sb_resp_intr", |
| "mrsb_resp_intr", |
| "core_dw_status_0", |
| "core_dw_status_1", |
| "core_dw_status_2", |
| "core_dw_status_3", |
| "core_dw_status_4", |
| "core_dw_status_5", |
| "core_dw_status_6", |
| "core_dw_status_7", |
| "async_arc2cpu_sei_intr", |
| }; |
| |
| static const char * const gaudi2_tpc_interrupts_cause[GAUDI2_NUM_OF_TPC_INTR_CAUSE] = { |
| "tpc_address_exceed_slm", |
| "tpc_div_by_0", |
| "tpc_spu_mac_overflow", |
| "tpc_spu_addsub_overflow", |
| "tpc_spu_abs_overflow", |
| "tpc_spu_fma_fp_dst_nan", |
| "tpc_spu_fma_fp_dst_inf", |
| "tpc_spu_convert_fp_dst_nan", |
| "tpc_spu_convert_fp_dst_inf", |
| "tpc_spu_fp_dst_denorm", |
| "tpc_vpu_mac_overflow", |
| "tpc_vpu_addsub_overflow", |
| "tpc_vpu_abs_overflow", |
| "tpc_vpu_convert_fp_dst_nan", |
| "tpc_vpu_convert_fp_dst_inf", |
| "tpc_vpu_fma_fp_dst_nan", |
| "tpc_vpu_fma_fp_dst_inf", |
| "tpc_vpu_fp_dst_denorm", |
| "tpc_assertions", |
| "tpc_illegal_instruction", |
| "tpc_pc_wrap_around", |
| "tpc_qm_sw_err", |
| "tpc_hbw_rresp_err", |
| "tpc_hbw_bresp_err", |
| "tpc_lbw_rresp_err", |
| "tpc_lbw_bresp_err", |
| "st_unlock_already_locked", |
| "invalid_lock_access", |
| "LD_L protection violation", |
| "ST_L protection violation", |
| "D$ L0CS mismatch", |
| }; |
| |
| static const char * const guadi2_mme_error_cause[GAUDI2_NUM_OF_MME_ERR_CAUSE] = { |
| "agu_resp_intr", |
| "qman_axi_err", |
| "wap sei (wbc axi err)", |
| "arc sei", |
| "cfg access error", |
| "qm_sw_err", |
| "sbte_dbg_intr_0", |
| "sbte_dbg_intr_1", |
| "sbte_dbg_intr_2", |
| "sbte_dbg_intr_3", |
| "sbte_dbg_intr_4", |
| "sbte_prtn_intr_0", |
| "sbte_prtn_intr_1", |
| "sbte_prtn_intr_2", |
| "sbte_prtn_intr_3", |
| "sbte_prtn_intr_4", |
| }; |
| |
| static const char * const guadi2_mme_wap_error_cause[GAUDI2_NUM_OF_MME_WAP_ERR_CAUSE] = { |
| "WBC ERR RESP_0", |
| "WBC ERR RESP_1", |
| "AP SOURCE POS INF", |
| "AP SOURCE NEG INF", |
| "AP SOURCE NAN", |
| "AP RESULT POS INF", |
| "AP RESULT NEG INF", |
| }; |
| |
| static const char * const gaudi2_dma_core_interrupts_cause[GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE] = { |
| "HBW Read returned with error RRESP", |
| "HBW write returned with error BRESP", |
| "LBW write returned with error BRESP", |
| "descriptor_fifo_overflow", |
| "KDMA SB LBW Read returned with error", |
| "KDMA WBC LBW Write returned with error", |
| "TRANSPOSE ENGINE DESC FIFO OVERFLOW", |
| "WRONG CFG FOR COMMIT IN LIN DMA" |
| }; |
| |
| static const char * const gaudi2_kdma_core_interrupts_cause[GAUDI2_NUM_OF_DMA_CORE_INTR_CAUSE] = { |
| "HBW/LBW Read returned with error RRESP", |
| "HBW/LBW write returned with error BRESP", |
| "LBW write returned with error BRESP", |
| "descriptor_fifo_overflow", |
| "KDMA SB LBW Read returned with error", |
| "KDMA WBC LBW Write returned with error", |
| "TRANSPOSE ENGINE DESC FIFO OVERFLOW", |
| "WRONG CFG FOR COMMIT IN LIN DMA" |
| }; |
| |
| struct gaudi2_sm_sei_cause_data { |
| const char *cause_name; |
| const char *log_name; |
| }; |
| |
| static const struct gaudi2_sm_sei_cause_data |
| gaudi2_sm_sei_cause[GAUDI2_NUM_OF_SM_SEI_ERR_CAUSE] = { |
| {"calculated SO value overflow/underflow", "SOB ID"}, |
| {"payload address of monitor is not aligned to 4B", "monitor addr"}, |
| {"armed monitor write got BRESP (SLVERR or DECERR)", "AXI id"}, |
| }; |
| |
| static const char * const |
| gaudi2_pmmu_fatal_interrupts_cause[GAUDI2_NUM_OF_PMMU_FATAL_ERR_CAUSE] = { |
| "LATENCY_RD_OUT_FIFO_OVERRUN", |
| "LATENCY_WR_OUT_FIFO_OVERRUN", |
| }; |
| |
| static const char * const |
| gaudi2_hif_fatal_interrupts_cause[GAUDI2_NUM_OF_HIF_FATAL_ERR_CAUSE] = { |
| "LATENCY_RD_OUT_FIFO_OVERRUN", |
| "LATENCY_WR_OUT_FIFO_OVERRUN", |
| }; |
| |
| static const char * const |
| gaudi2_psoc_axi_drain_interrupts_cause[GAUDI2_NUM_OF_AXI_DRAIN_ERR_CAUSE] = { |
| "AXI drain HBW", |
| "AXI drain LBW", |
| }; |
| |
| static const char * const |
| gaudi2_pcie_addr_dec_error_cause[GAUDI2_NUM_OF_PCIE_ADDR_DEC_ERR_CAUSE] = { |
| "HBW error response", |
| "LBW error response", |
| "TLP is blocked by RR" |
| }; |
| |
| static const int gaudi2_queue_id_to_engine_id[] = { |
| [GAUDI2_QUEUE_ID_PDMA_0_0...GAUDI2_QUEUE_ID_PDMA_0_3] = GAUDI2_ENGINE_ID_PDMA_0, |
| [GAUDI2_QUEUE_ID_PDMA_1_0...GAUDI2_QUEUE_ID_PDMA_1_3] = GAUDI2_ENGINE_ID_PDMA_1, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3] = |
| GAUDI2_DCORE0_ENGINE_ID_EDMA_0, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0...GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3] = |
| GAUDI2_DCORE0_ENGINE_ID_EDMA_1, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3] = |
| GAUDI2_DCORE1_ENGINE_ID_EDMA_0, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0...GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3] = |
| GAUDI2_DCORE1_ENGINE_ID_EDMA_1, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3] = |
| GAUDI2_DCORE2_ENGINE_ID_EDMA_0, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0...GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3] = |
| GAUDI2_DCORE2_ENGINE_ID_EDMA_1, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3] = |
| GAUDI2_DCORE3_ENGINE_ID_EDMA_0, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0...GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3] = |
| GAUDI2_DCORE3_ENGINE_ID_EDMA_1, |
| [GAUDI2_QUEUE_ID_DCORE0_MME_0_0...GAUDI2_QUEUE_ID_DCORE0_MME_0_3] = |
| GAUDI2_DCORE0_ENGINE_ID_MME, |
| [GAUDI2_QUEUE_ID_DCORE1_MME_0_0...GAUDI2_QUEUE_ID_DCORE1_MME_0_3] = |
| GAUDI2_DCORE1_ENGINE_ID_MME, |
| [GAUDI2_QUEUE_ID_DCORE2_MME_0_0...GAUDI2_QUEUE_ID_DCORE2_MME_0_3] = |
| GAUDI2_DCORE2_ENGINE_ID_MME, |
| [GAUDI2_QUEUE_ID_DCORE3_MME_0_0...GAUDI2_QUEUE_ID_DCORE3_MME_0_3] = |
| GAUDI2_DCORE3_ENGINE_ID_MME, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_0_0...GAUDI2_QUEUE_ID_DCORE0_TPC_0_3] = |
| GAUDI2_DCORE0_ENGINE_ID_TPC_0, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_1_0...GAUDI2_QUEUE_ID_DCORE0_TPC_1_3] = |
| GAUDI2_DCORE0_ENGINE_ID_TPC_1, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_2_0...GAUDI2_QUEUE_ID_DCORE0_TPC_2_3] = |
| GAUDI2_DCORE0_ENGINE_ID_TPC_2, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_3_0...GAUDI2_QUEUE_ID_DCORE0_TPC_3_3] = |
| GAUDI2_DCORE0_ENGINE_ID_TPC_3, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_4_0...GAUDI2_QUEUE_ID_DCORE0_TPC_4_3] = |
| GAUDI2_DCORE0_ENGINE_ID_TPC_4, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_5_0...GAUDI2_QUEUE_ID_DCORE0_TPC_5_3] = |
| GAUDI2_DCORE0_ENGINE_ID_TPC_5, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_6_0...GAUDI2_QUEUE_ID_DCORE0_TPC_6_3] = |
| GAUDI2_DCORE0_ENGINE_ID_TPC_6, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_0_0...GAUDI2_QUEUE_ID_DCORE1_TPC_0_3] = |
| GAUDI2_DCORE1_ENGINE_ID_TPC_0, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_1_0...GAUDI2_QUEUE_ID_DCORE1_TPC_1_3] = |
| GAUDI2_DCORE1_ENGINE_ID_TPC_1, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_2_0...GAUDI2_QUEUE_ID_DCORE1_TPC_2_3] = |
| GAUDI2_DCORE1_ENGINE_ID_TPC_2, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_3_0...GAUDI2_QUEUE_ID_DCORE1_TPC_3_3] = |
| GAUDI2_DCORE1_ENGINE_ID_TPC_3, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_4_0...GAUDI2_QUEUE_ID_DCORE1_TPC_4_3] = |
| GAUDI2_DCORE1_ENGINE_ID_TPC_4, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_5_0...GAUDI2_QUEUE_ID_DCORE1_TPC_5_3] = |
| GAUDI2_DCORE1_ENGINE_ID_TPC_5, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_0_0...GAUDI2_QUEUE_ID_DCORE2_TPC_0_3] = |
| GAUDI2_DCORE2_ENGINE_ID_TPC_0, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_1_0...GAUDI2_QUEUE_ID_DCORE2_TPC_1_3] = |
| GAUDI2_DCORE2_ENGINE_ID_TPC_1, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_2_0...GAUDI2_QUEUE_ID_DCORE2_TPC_2_3] = |
| GAUDI2_DCORE2_ENGINE_ID_TPC_2, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_3_0...GAUDI2_QUEUE_ID_DCORE2_TPC_3_3] = |
| GAUDI2_DCORE2_ENGINE_ID_TPC_3, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_4_0...GAUDI2_QUEUE_ID_DCORE2_TPC_4_3] = |
| GAUDI2_DCORE2_ENGINE_ID_TPC_4, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_5_0...GAUDI2_QUEUE_ID_DCORE2_TPC_5_3] = |
| GAUDI2_DCORE2_ENGINE_ID_TPC_5, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_0_0...GAUDI2_QUEUE_ID_DCORE3_TPC_0_3] = |
| GAUDI2_DCORE3_ENGINE_ID_TPC_0, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_1_0...GAUDI2_QUEUE_ID_DCORE3_TPC_1_3] = |
| GAUDI2_DCORE3_ENGINE_ID_TPC_1, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_2_0...GAUDI2_QUEUE_ID_DCORE3_TPC_2_3] = |
| GAUDI2_DCORE3_ENGINE_ID_TPC_2, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_3_0...GAUDI2_QUEUE_ID_DCORE3_TPC_3_3] = |
| GAUDI2_DCORE3_ENGINE_ID_TPC_3, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_4_0...GAUDI2_QUEUE_ID_DCORE3_TPC_4_3] = |
| GAUDI2_DCORE3_ENGINE_ID_TPC_4, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_5_0...GAUDI2_QUEUE_ID_DCORE3_TPC_5_3] = |
| GAUDI2_DCORE3_ENGINE_ID_TPC_5, |
| [GAUDI2_QUEUE_ID_NIC_0_0...GAUDI2_QUEUE_ID_NIC_0_3] = GAUDI2_ENGINE_ID_NIC0_0, |
| [GAUDI2_QUEUE_ID_NIC_1_0...GAUDI2_QUEUE_ID_NIC_1_3] = GAUDI2_ENGINE_ID_NIC0_1, |
| [GAUDI2_QUEUE_ID_NIC_2_0...GAUDI2_QUEUE_ID_NIC_2_3] = GAUDI2_ENGINE_ID_NIC1_0, |
| [GAUDI2_QUEUE_ID_NIC_3_0...GAUDI2_QUEUE_ID_NIC_3_3] = GAUDI2_ENGINE_ID_NIC1_1, |
| [GAUDI2_QUEUE_ID_NIC_4_0...GAUDI2_QUEUE_ID_NIC_4_3] = GAUDI2_ENGINE_ID_NIC2_0, |
| [GAUDI2_QUEUE_ID_NIC_5_0...GAUDI2_QUEUE_ID_NIC_5_3] = GAUDI2_ENGINE_ID_NIC2_1, |
| [GAUDI2_QUEUE_ID_NIC_6_0...GAUDI2_QUEUE_ID_NIC_6_3] = GAUDI2_ENGINE_ID_NIC3_0, |
| [GAUDI2_QUEUE_ID_NIC_7_0...GAUDI2_QUEUE_ID_NIC_7_3] = GAUDI2_ENGINE_ID_NIC3_1, |
| [GAUDI2_QUEUE_ID_NIC_8_0...GAUDI2_QUEUE_ID_NIC_8_3] = GAUDI2_ENGINE_ID_NIC4_0, |
| [GAUDI2_QUEUE_ID_NIC_9_0...GAUDI2_QUEUE_ID_NIC_9_3] = GAUDI2_ENGINE_ID_NIC4_1, |
| [GAUDI2_QUEUE_ID_NIC_10_0...GAUDI2_QUEUE_ID_NIC_10_3] = GAUDI2_ENGINE_ID_NIC5_0, |
| [GAUDI2_QUEUE_ID_NIC_11_0...GAUDI2_QUEUE_ID_NIC_11_3] = GAUDI2_ENGINE_ID_NIC5_1, |
| [GAUDI2_QUEUE_ID_NIC_12_0...GAUDI2_QUEUE_ID_NIC_12_3] = GAUDI2_ENGINE_ID_NIC6_0, |
| [GAUDI2_QUEUE_ID_NIC_13_0...GAUDI2_QUEUE_ID_NIC_13_3] = GAUDI2_ENGINE_ID_NIC6_1, |
| [GAUDI2_QUEUE_ID_NIC_14_0...GAUDI2_QUEUE_ID_NIC_14_3] = GAUDI2_ENGINE_ID_NIC7_0, |
| [GAUDI2_QUEUE_ID_NIC_15_0...GAUDI2_QUEUE_ID_NIC_15_3] = GAUDI2_ENGINE_ID_NIC7_1, |
| [GAUDI2_QUEUE_ID_NIC_16_0...GAUDI2_QUEUE_ID_NIC_16_3] = GAUDI2_ENGINE_ID_NIC8_0, |
| [GAUDI2_QUEUE_ID_NIC_17_0...GAUDI2_QUEUE_ID_NIC_17_3] = GAUDI2_ENGINE_ID_NIC8_1, |
| [GAUDI2_QUEUE_ID_NIC_18_0...GAUDI2_QUEUE_ID_NIC_18_3] = GAUDI2_ENGINE_ID_NIC9_0, |
| [GAUDI2_QUEUE_ID_NIC_19_0...GAUDI2_QUEUE_ID_NIC_19_3] = GAUDI2_ENGINE_ID_NIC9_1, |
| [GAUDI2_QUEUE_ID_NIC_20_0...GAUDI2_QUEUE_ID_NIC_20_3] = GAUDI2_ENGINE_ID_NIC10_0, |
| [GAUDI2_QUEUE_ID_NIC_21_0...GAUDI2_QUEUE_ID_NIC_21_3] = GAUDI2_ENGINE_ID_NIC10_1, |
| [GAUDI2_QUEUE_ID_NIC_22_0...GAUDI2_QUEUE_ID_NIC_22_3] = GAUDI2_ENGINE_ID_NIC11_0, |
| [GAUDI2_QUEUE_ID_NIC_23_0...GAUDI2_QUEUE_ID_NIC_23_3] = GAUDI2_ENGINE_ID_NIC11_1, |
| [GAUDI2_QUEUE_ID_ROT_0_0...GAUDI2_QUEUE_ID_ROT_0_3] = GAUDI2_ENGINE_ID_ROT_0, |
| [GAUDI2_QUEUE_ID_ROT_1_0...GAUDI2_QUEUE_ID_ROT_1_3] = GAUDI2_ENGINE_ID_ROT_1, |
| }; |
| |
| const u32 gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_SIZE] = { |
| [GAUDI2_QUEUE_ID_PDMA_0_0] = mmPDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_PDMA_0_1] = mmPDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_PDMA_0_2] = mmPDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_PDMA_0_3] = mmPDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_PDMA_1_0] = mmPDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_PDMA_1_1] = mmPDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_PDMA_1_2] = mmPDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_PDMA_1_3] = mmPDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0] = mmDCORE0_EDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1] = mmDCORE0_EDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2] = mmDCORE0_EDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3] = mmDCORE0_EDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0] = mmDCORE0_EDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1] = mmDCORE0_EDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2] = mmDCORE0_EDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3] = mmDCORE0_EDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_MME_0_0] = mmDCORE0_MME_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_MME_0_1] = mmDCORE0_MME_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_MME_0_2] = mmDCORE0_MME_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_MME_0_3] = mmDCORE0_MME_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_0_0] = mmDCORE0_TPC0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_0_1] = mmDCORE0_TPC0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_0_2] = mmDCORE0_TPC0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_0_3] = mmDCORE0_TPC0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_1_0] = mmDCORE0_TPC1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_1_1] = mmDCORE0_TPC1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_1_2] = mmDCORE0_TPC1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_1_3] = mmDCORE0_TPC1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_2_0] = mmDCORE0_TPC2_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_2_1] = mmDCORE0_TPC2_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_2_2] = mmDCORE0_TPC2_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_2_3] = mmDCORE0_TPC2_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_3_0] = mmDCORE0_TPC3_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_3_1] = mmDCORE0_TPC3_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_3_2] = mmDCORE0_TPC3_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_3_3] = mmDCORE0_TPC3_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_4_0] = mmDCORE0_TPC4_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_4_1] = mmDCORE0_TPC4_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_4_2] = mmDCORE0_TPC4_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_4_3] = mmDCORE0_TPC4_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_5_0] = mmDCORE0_TPC5_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_5_1] = mmDCORE0_TPC5_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_5_2] = mmDCORE0_TPC5_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_5_3] = mmDCORE0_TPC5_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_6_0] = mmDCORE0_TPC6_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_6_1] = mmDCORE0_TPC6_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_6_2] = mmDCORE0_TPC6_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_6_3] = mmDCORE0_TPC6_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0] = mmDCORE1_EDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1] = mmDCORE1_EDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2] = mmDCORE1_EDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3] = mmDCORE1_EDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0] = mmDCORE1_EDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1] = mmDCORE1_EDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2] = mmDCORE1_EDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3] = mmDCORE1_EDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_MME_0_0] = mmDCORE1_MME_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_MME_0_1] = mmDCORE1_MME_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_MME_0_2] = mmDCORE1_MME_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_MME_0_3] = mmDCORE1_MME_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_0_0] = mmDCORE1_TPC0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_0_1] = mmDCORE1_TPC0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_0_2] = mmDCORE1_TPC0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_0_3] = mmDCORE1_TPC0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_1_0] = mmDCORE1_TPC1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_1_1] = mmDCORE1_TPC1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_1_2] = mmDCORE1_TPC1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_1_3] = mmDCORE1_TPC1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_2_0] = mmDCORE1_TPC2_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_2_1] = mmDCORE1_TPC2_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_2_2] = mmDCORE1_TPC2_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_2_3] = mmDCORE1_TPC2_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_3_0] = mmDCORE1_TPC3_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_3_1] = mmDCORE1_TPC3_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_3_2] = mmDCORE1_TPC3_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_3_3] = mmDCORE1_TPC3_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_4_0] = mmDCORE1_TPC4_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_4_1] = mmDCORE1_TPC4_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_4_2] = mmDCORE1_TPC4_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_4_3] = mmDCORE1_TPC4_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_5_0] = mmDCORE1_TPC5_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_5_1] = mmDCORE1_TPC5_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_5_2] = mmDCORE1_TPC5_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_5_3] = mmDCORE1_TPC5_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0] = mmDCORE2_EDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1] = mmDCORE2_EDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2] = mmDCORE2_EDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3] = mmDCORE2_EDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0] = mmDCORE2_EDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1] = mmDCORE2_EDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2] = mmDCORE2_EDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3] = mmDCORE2_EDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_MME_0_0] = mmDCORE2_MME_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_MME_0_1] = mmDCORE2_MME_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_MME_0_2] = mmDCORE2_MME_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_MME_0_3] = mmDCORE2_MME_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_0_0] = mmDCORE2_TPC0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_0_1] = mmDCORE2_TPC0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_0_2] = mmDCORE2_TPC0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_0_3] = mmDCORE2_TPC0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_1_0] = mmDCORE2_TPC1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_1_1] = mmDCORE2_TPC1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_1_2] = mmDCORE2_TPC1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_1_3] = mmDCORE2_TPC1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_2_0] = mmDCORE2_TPC2_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_2_1] = mmDCORE2_TPC2_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_2_2] = mmDCORE2_TPC2_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_2_3] = mmDCORE2_TPC2_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_3_0] = mmDCORE2_TPC3_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_3_1] = mmDCORE2_TPC3_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_3_2] = mmDCORE2_TPC3_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_3_3] = mmDCORE2_TPC3_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_4_0] = mmDCORE2_TPC4_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_4_1] = mmDCORE2_TPC4_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_4_2] = mmDCORE2_TPC4_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_4_3] = mmDCORE2_TPC4_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_5_0] = mmDCORE2_TPC5_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_5_1] = mmDCORE2_TPC5_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_5_2] = mmDCORE2_TPC5_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_5_3] = mmDCORE2_TPC5_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0] = mmDCORE3_EDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1] = mmDCORE3_EDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2] = mmDCORE3_EDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3] = mmDCORE3_EDMA0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0] = mmDCORE3_EDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1] = mmDCORE3_EDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2] = mmDCORE3_EDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3] = mmDCORE3_EDMA1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_MME_0_0] = mmDCORE3_MME_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_MME_0_1] = mmDCORE3_MME_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_MME_0_2] = mmDCORE3_MME_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_MME_0_3] = mmDCORE3_MME_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_0_0] = mmDCORE3_TPC0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_0_1] = mmDCORE3_TPC0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_0_2] = mmDCORE3_TPC0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_0_3] = mmDCORE3_TPC0_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_1_0] = mmDCORE3_TPC1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_1_1] = mmDCORE3_TPC1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_1_2] = mmDCORE3_TPC1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_1_3] = mmDCORE3_TPC1_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_2_0] = mmDCORE3_TPC2_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_2_1] = mmDCORE3_TPC2_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_2_2] = mmDCORE3_TPC2_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_2_3] = mmDCORE3_TPC2_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_3_0] = mmDCORE3_TPC3_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_3_1] = mmDCORE3_TPC3_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_3_2] = mmDCORE3_TPC3_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_3_3] = mmDCORE3_TPC3_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_4_0] = mmDCORE3_TPC4_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_4_1] = mmDCORE3_TPC4_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_4_2] = mmDCORE3_TPC4_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_4_3] = mmDCORE3_TPC4_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_5_0] = mmDCORE3_TPC5_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_5_1] = mmDCORE3_TPC5_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_5_2] = mmDCORE3_TPC5_QM_BASE, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_5_3] = mmDCORE3_TPC5_QM_BASE, |
| [GAUDI2_QUEUE_ID_NIC_0_0] = mmNIC0_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_0_1] = mmNIC0_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_0_2] = mmNIC0_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_0_3] = mmNIC0_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_1_0] = mmNIC0_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_1_1] = mmNIC0_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_1_2] = mmNIC0_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_1_3] = mmNIC0_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_2_0] = mmNIC1_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_2_1] = mmNIC1_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_2_2] = mmNIC1_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_2_3] = mmNIC1_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_3_0] = mmNIC1_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_3_1] = mmNIC1_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_3_2] = mmNIC1_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_3_3] = mmNIC1_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_4_0] = mmNIC2_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_4_1] = mmNIC2_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_4_2] = mmNIC2_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_4_3] = mmNIC2_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_5_0] = mmNIC2_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_5_1] = mmNIC2_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_5_2] = mmNIC2_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_5_3] = mmNIC2_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_6_0] = mmNIC3_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_6_1] = mmNIC3_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_6_2] = mmNIC3_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_6_3] = mmNIC3_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_7_0] = mmNIC3_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_7_1] = mmNIC3_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_7_2] = mmNIC3_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_7_3] = mmNIC3_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_8_0] = mmNIC4_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_8_1] = mmNIC4_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_8_2] = mmNIC4_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_8_3] = mmNIC4_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_9_0] = mmNIC4_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_9_1] = mmNIC4_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_9_2] = mmNIC4_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_9_3] = mmNIC4_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_10_0] = mmNIC5_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_10_1] = mmNIC5_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_10_2] = mmNIC5_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_10_3] = mmNIC5_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_11_0] = mmNIC5_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_11_1] = mmNIC5_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_11_2] = mmNIC5_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_11_3] = mmNIC5_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_12_0] = mmNIC6_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_12_1] = mmNIC6_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_12_2] = mmNIC6_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_12_3] = mmNIC6_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_13_0] = mmNIC6_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_13_1] = mmNIC6_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_13_2] = mmNIC6_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_13_3] = mmNIC6_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_14_0] = mmNIC7_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_14_1] = mmNIC7_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_14_2] = mmNIC7_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_14_3] = mmNIC7_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_15_0] = mmNIC7_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_15_1] = mmNIC7_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_15_2] = mmNIC7_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_15_3] = mmNIC7_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_16_0] = mmNIC8_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_16_1] = mmNIC8_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_16_2] = mmNIC8_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_16_3] = mmNIC8_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_17_0] = mmNIC8_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_17_1] = mmNIC8_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_17_2] = mmNIC8_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_17_3] = mmNIC8_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_18_0] = mmNIC9_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_18_1] = mmNIC9_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_18_2] = mmNIC9_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_18_3] = mmNIC9_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_19_0] = mmNIC9_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_19_1] = mmNIC9_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_19_2] = mmNIC9_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_19_3] = mmNIC9_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_20_0] = mmNIC10_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_20_1] = mmNIC10_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_20_2] = mmNIC10_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_20_3] = mmNIC10_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_21_0] = mmNIC10_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_21_1] = mmNIC10_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_21_2] = mmNIC10_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_21_3] = mmNIC10_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_22_0] = mmNIC11_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_22_1] = mmNIC11_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_22_2] = mmNIC11_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_22_3] = mmNIC11_QM0_BASE, |
| [GAUDI2_QUEUE_ID_NIC_23_0] = mmNIC11_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_23_1] = mmNIC11_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_23_2] = mmNIC11_QM1_BASE, |
| [GAUDI2_QUEUE_ID_NIC_23_3] = mmNIC11_QM1_BASE, |
| [GAUDI2_QUEUE_ID_ROT_0_0] = mmROT0_QM_BASE, |
| [GAUDI2_QUEUE_ID_ROT_0_1] = mmROT0_QM_BASE, |
| [GAUDI2_QUEUE_ID_ROT_0_2] = mmROT0_QM_BASE, |
| [GAUDI2_QUEUE_ID_ROT_0_3] = mmROT0_QM_BASE, |
| [GAUDI2_QUEUE_ID_ROT_1_0] = mmROT1_QM_BASE, |
| [GAUDI2_QUEUE_ID_ROT_1_1] = mmROT1_QM_BASE, |
| [GAUDI2_QUEUE_ID_ROT_1_2] = mmROT1_QM_BASE, |
| [GAUDI2_QUEUE_ID_ROT_1_3] = mmROT1_QM_BASE |
| }; |
| |
| static const u32 gaudi2_arc_blocks_bases[NUM_ARC_CPUS] = { |
| [CPU_ID_SCHED_ARC0] = mmARC_FARM_ARC0_AUX_BASE, |
| [CPU_ID_SCHED_ARC1] = mmARC_FARM_ARC1_AUX_BASE, |
| [CPU_ID_SCHED_ARC2] = mmARC_FARM_ARC2_AUX_BASE, |
| [CPU_ID_SCHED_ARC3] = mmARC_FARM_ARC3_AUX_BASE, |
| [CPU_ID_SCHED_ARC4] = mmDCORE1_MME_QM_ARC_AUX_BASE, |
| [CPU_ID_SCHED_ARC5] = mmDCORE3_MME_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC0] = mmDCORE0_TPC0_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC1] = mmDCORE0_TPC1_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC2] = mmDCORE0_TPC2_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC3] = mmDCORE0_TPC3_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC4] = mmDCORE0_TPC4_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC5] = mmDCORE0_TPC5_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC6] = mmDCORE1_TPC0_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC7] = mmDCORE1_TPC1_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC8] = mmDCORE1_TPC2_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC9] = mmDCORE1_TPC3_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC10] = mmDCORE1_TPC4_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC11] = mmDCORE1_TPC5_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC12] = mmDCORE2_TPC0_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC13] = mmDCORE2_TPC1_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC14] = mmDCORE2_TPC2_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC15] = mmDCORE2_TPC3_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC16] = mmDCORE2_TPC4_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC17] = mmDCORE2_TPC5_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC18] = mmDCORE3_TPC0_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC19] = mmDCORE3_TPC1_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC20] = mmDCORE3_TPC2_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC21] = mmDCORE3_TPC3_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC22] = mmDCORE3_TPC4_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC23] = mmDCORE3_TPC5_QM_ARC_AUX_BASE, |
| [CPU_ID_TPC_QMAN_ARC24] = mmDCORE0_TPC6_QM_ARC_AUX_BASE, |
| [CPU_ID_MME_QMAN_ARC0] = mmDCORE0_MME_QM_ARC_AUX_BASE, |
| [CPU_ID_MME_QMAN_ARC1] = mmDCORE2_MME_QM_ARC_AUX_BASE, |
| [CPU_ID_EDMA_QMAN_ARC0] = mmDCORE0_EDMA0_QM_ARC_AUX_BASE, |
| [CPU_ID_EDMA_QMAN_ARC1] = mmDCORE0_EDMA1_QM_ARC_AUX_BASE, |
| [CPU_ID_EDMA_QMAN_ARC2] = mmDCORE1_EDMA0_QM_ARC_AUX_BASE, |
| [CPU_ID_EDMA_QMAN_ARC3] = mmDCORE1_EDMA1_QM_ARC_AUX_BASE, |
| [CPU_ID_EDMA_QMAN_ARC4] = mmDCORE2_EDMA0_QM_ARC_AUX_BASE, |
| [CPU_ID_EDMA_QMAN_ARC5] = mmDCORE2_EDMA1_QM_ARC_AUX_BASE, |
| [CPU_ID_EDMA_QMAN_ARC6] = mmDCORE3_EDMA0_QM_ARC_AUX_BASE, |
| [CPU_ID_EDMA_QMAN_ARC7] = mmDCORE3_EDMA1_QM_ARC_AUX_BASE, |
| [CPU_ID_PDMA_QMAN_ARC0] = mmPDMA0_QM_ARC_AUX_BASE, |
| [CPU_ID_PDMA_QMAN_ARC1] = mmPDMA1_QM_ARC_AUX_BASE, |
| [CPU_ID_ROT_QMAN_ARC0] = mmROT0_QM_ARC_AUX_BASE, |
| [CPU_ID_ROT_QMAN_ARC1] = mmROT1_QM_ARC_AUX_BASE, |
| [CPU_ID_NIC_QMAN_ARC0] = mmNIC0_QM_ARC_AUX0_BASE, |
| [CPU_ID_NIC_QMAN_ARC1] = mmNIC0_QM_ARC_AUX1_BASE, |
| [CPU_ID_NIC_QMAN_ARC2] = mmNIC1_QM_ARC_AUX0_BASE, |
| [CPU_ID_NIC_QMAN_ARC3] = mmNIC1_QM_ARC_AUX1_BASE, |
| [CPU_ID_NIC_QMAN_ARC4] = mmNIC2_QM_ARC_AUX0_BASE, |
| [CPU_ID_NIC_QMAN_ARC5] = mmNIC2_QM_ARC_AUX1_BASE, |
| [CPU_ID_NIC_QMAN_ARC6] = mmNIC3_QM_ARC_AUX0_BASE, |
| [CPU_ID_NIC_QMAN_ARC7] = mmNIC3_QM_ARC_AUX1_BASE, |
| [CPU_ID_NIC_QMAN_ARC8] = mmNIC4_QM_ARC_AUX0_BASE, |
| [CPU_ID_NIC_QMAN_ARC9] = mmNIC4_QM_ARC_AUX1_BASE, |
| [CPU_ID_NIC_QMAN_ARC10] = mmNIC5_QM_ARC_AUX0_BASE, |
| [CPU_ID_NIC_QMAN_ARC11] = mmNIC5_QM_ARC_AUX1_BASE, |
| [CPU_ID_NIC_QMAN_ARC12] = mmNIC6_QM_ARC_AUX0_BASE, |
| [CPU_ID_NIC_QMAN_ARC13] = mmNIC6_QM_ARC_AUX1_BASE, |
| [CPU_ID_NIC_QMAN_ARC14] = mmNIC7_QM_ARC_AUX0_BASE, |
| [CPU_ID_NIC_QMAN_ARC15] = mmNIC7_QM_ARC_AUX1_BASE, |
| [CPU_ID_NIC_QMAN_ARC16] = mmNIC8_QM_ARC_AUX0_BASE, |
| [CPU_ID_NIC_QMAN_ARC17] = mmNIC8_QM_ARC_AUX1_BASE, |
| [CPU_ID_NIC_QMAN_ARC18] = mmNIC9_QM_ARC_AUX0_BASE, |
| [CPU_ID_NIC_QMAN_ARC19] = mmNIC9_QM_ARC_AUX1_BASE, |
| [CPU_ID_NIC_QMAN_ARC20] = mmNIC10_QM_ARC_AUX0_BASE, |
| [CPU_ID_NIC_QMAN_ARC21] = mmNIC10_QM_ARC_AUX1_BASE, |
| [CPU_ID_NIC_QMAN_ARC22] = mmNIC11_QM_ARC_AUX0_BASE, |
| [CPU_ID_NIC_QMAN_ARC23] = mmNIC11_QM_ARC_AUX1_BASE, |
| }; |
| |
| static const u32 gaudi2_arc_dccm_bases[NUM_ARC_CPUS] = { |
| [CPU_ID_SCHED_ARC0] = mmARC_FARM_ARC0_DCCM0_BASE, |
| [CPU_ID_SCHED_ARC1] = mmARC_FARM_ARC1_DCCM0_BASE, |
| [CPU_ID_SCHED_ARC2] = mmARC_FARM_ARC2_DCCM0_BASE, |
| [CPU_ID_SCHED_ARC3] = mmARC_FARM_ARC3_DCCM0_BASE, |
| [CPU_ID_SCHED_ARC4] = mmDCORE1_MME_QM_ARC_DCCM_BASE, |
| [CPU_ID_SCHED_ARC5] = mmDCORE3_MME_QM_ARC_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC0] = mmDCORE0_TPC0_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC1] = mmDCORE0_TPC1_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC2] = mmDCORE0_TPC2_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC3] = mmDCORE0_TPC3_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC4] = mmDCORE0_TPC4_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC5] = mmDCORE0_TPC5_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC6] = mmDCORE1_TPC0_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC7] = mmDCORE1_TPC1_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC8] = mmDCORE1_TPC2_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC9] = mmDCORE1_TPC3_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC10] = mmDCORE1_TPC4_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC11] = mmDCORE1_TPC5_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC12] = mmDCORE2_TPC0_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC13] = mmDCORE2_TPC1_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC14] = mmDCORE2_TPC2_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC15] = mmDCORE2_TPC3_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC16] = mmDCORE2_TPC4_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC17] = mmDCORE2_TPC5_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC18] = mmDCORE3_TPC0_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC19] = mmDCORE3_TPC1_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC20] = mmDCORE3_TPC2_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC21] = mmDCORE3_TPC3_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC22] = mmDCORE3_TPC4_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC23] = mmDCORE3_TPC5_QM_DCCM_BASE, |
| [CPU_ID_TPC_QMAN_ARC24] = mmDCORE0_TPC6_QM_DCCM_BASE, |
| [CPU_ID_MME_QMAN_ARC0] = mmDCORE0_MME_QM_ARC_DCCM_BASE, |
| [CPU_ID_MME_QMAN_ARC1] = mmDCORE2_MME_QM_ARC_DCCM_BASE, |
| [CPU_ID_EDMA_QMAN_ARC0] = mmDCORE0_EDMA0_QM_DCCM_BASE, |
| [CPU_ID_EDMA_QMAN_ARC1] = mmDCORE0_EDMA1_QM_DCCM_BASE, |
| [CPU_ID_EDMA_QMAN_ARC2] = mmDCORE1_EDMA0_QM_DCCM_BASE, |
| [CPU_ID_EDMA_QMAN_ARC3] = mmDCORE1_EDMA1_QM_DCCM_BASE, |
| [CPU_ID_EDMA_QMAN_ARC4] = mmDCORE2_EDMA0_QM_DCCM_BASE, |
| [CPU_ID_EDMA_QMAN_ARC5] = mmDCORE2_EDMA1_QM_DCCM_BASE, |
| [CPU_ID_EDMA_QMAN_ARC6] = mmDCORE3_EDMA0_QM_DCCM_BASE, |
| [CPU_ID_EDMA_QMAN_ARC7] = mmDCORE3_EDMA1_QM_DCCM_BASE, |
| [CPU_ID_PDMA_QMAN_ARC0] = mmPDMA0_QM_ARC_DCCM_BASE, |
| [CPU_ID_PDMA_QMAN_ARC1] = mmPDMA1_QM_ARC_DCCM_BASE, |
| [CPU_ID_ROT_QMAN_ARC0] = mmROT0_QM_ARC_DCCM_BASE, |
| [CPU_ID_ROT_QMAN_ARC1] = mmROT1_QM_ARC_DCCM_BASE, |
| [CPU_ID_NIC_QMAN_ARC0] = mmNIC0_QM_DCCM0_BASE, |
| [CPU_ID_NIC_QMAN_ARC1] = mmNIC0_QM_DCCM1_BASE, |
| [CPU_ID_NIC_QMAN_ARC2] = mmNIC1_QM_DCCM0_BASE, |
| [CPU_ID_NIC_QMAN_ARC3] = mmNIC1_QM_DCCM1_BASE, |
| [CPU_ID_NIC_QMAN_ARC4] = mmNIC2_QM_DCCM0_BASE, |
| [CPU_ID_NIC_QMAN_ARC5] = mmNIC2_QM_DCCM1_BASE, |
| [CPU_ID_NIC_QMAN_ARC6] = mmNIC3_QM_DCCM0_BASE, |
| [CPU_ID_NIC_QMAN_ARC7] = mmNIC3_QM_DCCM1_BASE, |
| [CPU_ID_NIC_QMAN_ARC8] = mmNIC4_QM_DCCM0_BASE, |
| [CPU_ID_NIC_QMAN_ARC9] = mmNIC4_QM_DCCM1_BASE, |
| [CPU_ID_NIC_QMAN_ARC10] = mmNIC5_QM_DCCM0_BASE, |
| [CPU_ID_NIC_QMAN_ARC11] = mmNIC5_QM_DCCM1_BASE, |
| [CPU_ID_NIC_QMAN_ARC12] = mmNIC6_QM_DCCM0_BASE, |
| [CPU_ID_NIC_QMAN_ARC13] = mmNIC6_QM_DCCM1_BASE, |
| [CPU_ID_NIC_QMAN_ARC14] = mmNIC7_QM_DCCM0_BASE, |
| [CPU_ID_NIC_QMAN_ARC15] = mmNIC7_QM_DCCM1_BASE, |
| [CPU_ID_NIC_QMAN_ARC16] = mmNIC8_QM_DCCM0_BASE, |
| [CPU_ID_NIC_QMAN_ARC17] = mmNIC8_QM_DCCM1_BASE, |
| [CPU_ID_NIC_QMAN_ARC18] = mmNIC9_QM_DCCM0_BASE, |
| [CPU_ID_NIC_QMAN_ARC19] = mmNIC9_QM_DCCM1_BASE, |
| [CPU_ID_NIC_QMAN_ARC20] = mmNIC10_QM_DCCM0_BASE, |
| [CPU_ID_NIC_QMAN_ARC21] = mmNIC10_QM_DCCM1_BASE, |
| [CPU_ID_NIC_QMAN_ARC22] = mmNIC11_QM_DCCM0_BASE, |
| [CPU_ID_NIC_QMAN_ARC23] = mmNIC11_QM_DCCM1_BASE, |
| }; |
| |
| const u32 gaudi2_mme_ctrl_lo_blocks_bases[MME_ID_SIZE] = { |
| [MME_ID_DCORE0] = mmDCORE0_MME_CTRL_LO_BASE, |
| [MME_ID_DCORE1] = mmDCORE1_MME_CTRL_LO_BASE, |
| [MME_ID_DCORE2] = mmDCORE2_MME_CTRL_LO_BASE, |
| [MME_ID_DCORE3] = mmDCORE3_MME_CTRL_LO_BASE, |
| }; |
| |
| static const u32 gaudi2_queue_id_to_arc_id[GAUDI2_QUEUE_ID_SIZE] = { |
| [GAUDI2_QUEUE_ID_PDMA_0_0] = CPU_ID_PDMA_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_PDMA_0_1] = CPU_ID_PDMA_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_PDMA_0_2] = CPU_ID_PDMA_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_PDMA_0_3] = CPU_ID_PDMA_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_PDMA_1_0] = CPU_ID_PDMA_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_PDMA_1_1] = CPU_ID_PDMA_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_PDMA_1_2] = CPU_ID_PDMA_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_PDMA_1_3] = CPU_ID_PDMA_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0] = CPU_ID_EDMA_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1] = CPU_ID_EDMA_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2] = CPU_ID_EDMA_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3] = CPU_ID_EDMA_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0] = CPU_ID_EDMA_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1] = CPU_ID_EDMA_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2] = CPU_ID_EDMA_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3] = CPU_ID_EDMA_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_DCORE0_MME_0_0] = CPU_ID_MME_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_DCORE0_MME_0_1] = CPU_ID_MME_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_DCORE0_MME_0_2] = CPU_ID_MME_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_DCORE0_MME_0_3] = CPU_ID_MME_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_0_0] = CPU_ID_TPC_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_0_1] = CPU_ID_TPC_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_0_2] = CPU_ID_TPC_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_0_3] = CPU_ID_TPC_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_1_0] = CPU_ID_TPC_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_1_1] = CPU_ID_TPC_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_1_2] = CPU_ID_TPC_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_1_3] = CPU_ID_TPC_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_2_0] = CPU_ID_TPC_QMAN_ARC2, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_2_1] = CPU_ID_TPC_QMAN_ARC2, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_2_2] = CPU_ID_TPC_QMAN_ARC2, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_2_3] = CPU_ID_TPC_QMAN_ARC2, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_3_0] = CPU_ID_TPC_QMAN_ARC3, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_3_1] = CPU_ID_TPC_QMAN_ARC3, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_3_2] = CPU_ID_TPC_QMAN_ARC3, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_3_3] = CPU_ID_TPC_QMAN_ARC3, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_4_0] = CPU_ID_TPC_QMAN_ARC4, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_4_1] = CPU_ID_TPC_QMAN_ARC4, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_4_2] = CPU_ID_TPC_QMAN_ARC4, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_4_3] = CPU_ID_TPC_QMAN_ARC4, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_5_0] = CPU_ID_TPC_QMAN_ARC5, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_5_1] = CPU_ID_TPC_QMAN_ARC5, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_5_2] = CPU_ID_TPC_QMAN_ARC5, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_5_3] = CPU_ID_TPC_QMAN_ARC5, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_6_0] = CPU_ID_TPC_QMAN_ARC24, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_6_1] = CPU_ID_TPC_QMAN_ARC24, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_6_2] = CPU_ID_TPC_QMAN_ARC24, |
| [GAUDI2_QUEUE_ID_DCORE0_TPC_6_3] = CPU_ID_TPC_QMAN_ARC24, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0] = CPU_ID_EDMA_QMAN_ARC2, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1] = CPU_ID_EDMA_QMAN_ARC2, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2] = CPU_ID_EDMA_QMAN_ARC2, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3] = CPU_ID_EDMA_QMAN_ARC2, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0] = CPU_ID_EDMA_QMAN_ARC3, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1] = CPU_ID_EDMA_QMAN_ARC3, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2] = CPU_ID_EDMA_QMAN_ARC3, |
| [GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3] = CPU_ID_EDMA_QMAN_ARC3, |
| [GAUDI2_QUEUE_ID_DCORE1_MME_0_0] = CPU_ID_SCHED_ARC4, |
| [GAUDI2_QUEUE_ID_DCORE1_MME_0_1] = CPU_ID_SCHED_ARC4, |
| [GAUDI2_QUEUE_ID_DCORE1_MME_0_2] = CPU_ID_SCHED_ARC4, |
| [GAUDI2_QUEUE_ID_DCORE1_MME_0_3] = CPU_ID_SCHED_ARC4, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_0_0] = CPU_ID_TPC_QMAN_ARC6, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_0_1] = CPU_ID_TPC_QMAN_ARC6, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_0_2] = CPU_ID_TPC_QMAN_ARC6, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_0_3] = CPU_ID_TPC_QMAN_ARC6, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_1_0] = CPU_ID_TPC_QMAN_ARC7, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_1_1] = CPU_ID_TPC_QMAN_ARC7, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_1_2] = CPU_ID_TPC_QMAN_ARC7, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_1_3] = CPU_ID_TPC_QMAN_ARC7, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_2_0] = CPU_ID_TPC_QMAN_ARC8, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_2_1] = CPU_ID_TPC_QMAN_ARC8, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_2_2] = CPU_ID_TPC_QMAN_ARC8, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_2_3] = CPU_ID_TPC_QMAN_ARC8, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_3_0] = CPU_ID_TPC_QMAN_ARC9, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_3_1] = CPU_ID_TPC_QMAN_ARC9, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_3_2] = CPU_ID_TPC_QMAN_ARC9, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_3_3] = CPU_ID_TPC_QMAN_ARC9, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_4_0] = CPU_ID_TPC_QMAN_ARC10, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_4_1] = CPU_ID_TPC_QMAN_ARC10, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_4_2] = CPU_ID_TPC_QMAN_ARC10, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_4_3] = CPU_ID_TPC_QMAN_ARC10, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_5_0] = CPU_ID_TPC_QMAN_ARC11, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_5_1] = CPU_ID_TPC_QMAN_ARC11, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_5_2] = CPU_ID_TPC_QMAN_ARC11, |
| [GAUDI2_QUEUE_ID_DCORE1_TPC_5_3] = CPU_ID_TPC_QMAN_ARC11, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0] = CPU_ID_EDMA_QMAN_ARC4, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1] = CPU_ID_EDMA_QMAN_ARC4, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2] = CPU_ID_EDMA_QMAN_ARC4, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3] = CPU_ID_EDMA_QMAN_ARC4, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0] = CPU_ID_EDMA_QMAN_ARC5, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1] = CPU_ID_EDMA_QMAN_ARC5, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2] = CPU_ID_EDMA_QMAN_ARC5, |
| [GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3] = CPU_ID_EDMA_QMAN_ARC5, |
| [GAUDI2_QUEUE_ID_DCORE2_MME_0_0] = CPU_ID_MME_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_DCORE2_MME_0_1] = CPU_ID_MME_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_DCORE2_MME_0_2] = CPU_ID_MME_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_DCORE2_MME_0_3] = CPU_ID_MME_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_0_0] = CPU_ID_TPC_QMAN_ARC12, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_0_1] = CPU_ID_TPC_QMAN_ARC12, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_0_2] = CPU_ID_TPC_QMAN_ARC12, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_0_3] = CPU_ID_TPC_QMAN_ARC12, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_1_0] = CPU_ID_TPC_QMAN_ARC13, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_1_1] = CPU_ID_TPC_QMAN_ARC13, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_1_2] = CPU_ID_TPC_QMAN_ARC13, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_1_3] = CPU_ID_TPC_QMAN_ARC13, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_2_0] = CPU_ID_TPC_QMAN_ARC14, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_2_1] = CPU_ID_TPC_QMAN_ARC14, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_2_2] = CPU_ID_TPC_QMAN_ARC14, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_2_3] = CPU_ID_TPC_QMAN_ARC14, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_3_0] = CPU_ID_TPC_QMAN_ARC15, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_3_1] = CPU_ID_TPC_QMAN_ARC15, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_3_2] = CPU_ID_TPC_QMAN_ARC15, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_3_3] = CPU_ID_TPC_QMAN_ARC15, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_4_0] = CPU_ID_TPC_QMAN_ARC16, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_4_1] = CPU_ID_TPC_QMAN_ARC16, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_4_2] = CPU_ID_TPC_QMAN_ARC16, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_4_3] = CPU_ID_TPC_QMAN_ARC16, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_5_0] = CPU_ID_TPC_QMAN_ARC17, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_5_1] = CPU_ID_TPC_QMAN_ARC17, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_5_2] = CPU_ID_TPC_QMAN_ARC17, |
| [GAUDI2_QUEUE_ID_DCORE2_TPC_5_3] = CPU_ID_TPC_QMAN_ARC17, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0] = CPU_ID_EDMA_QMAN_ARC6, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1] = CPU_ID_EDMA_QMAN_ARC6, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2] = CPU_ID_EDMA_QMAN_ARC6, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3] = CPU_ID_EDMA_QMAN_ARC6, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0] = CPU_ID_EDMA_QMAN_ARC7, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1] = CPU_ID_EDMA_QMAN_ARC7, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2] = CPU_ID_EDMA_QMAN_ARC7, |
| [GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3] = CPU_ID_EDMA_QMAN_ARC7, |
| [GAUDI2_QUEUE_ID_DCORE3_MME_0_0] = CPU_ID_SCHED_ARC5, |
| [GAUDI2_QUEUE_ID_DCORE3_MME_0_1] = CPU_ID_SCHED_ARC5, |
| [GAUDI2_QUEUE_ID_DCORE3_MME_0_2] = CPU_ID_SCHED_ARC5, |
| [GAUDI2_QUEUE_ID_DCORE3_MME_0_3] = CPU_ID_SCHED_ARC5, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_0_0] = CPU_ID_TPC_QMAN_ARC18, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_0_1] = CPU_ID_TPC_QMAN_ARC18, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_0_2] = CPU_ID_TPC_QMAN_ARC18, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_0_3] = CPU_ID_TPC_QMAN_ARC18, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_1_0] = CPU_ID_TPC_QMAN_ARC19, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_1_1] = CPU_ID_TPC_QMAN_ARC19, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_1_2] = CPU_ID_TPC_QMAN_ARC19, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_1_3] = CPU_ID_TPC_QMAN_ARC19, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_2_0] = CPU_ID_TPC_QMAN_ARC20, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_2_1] = CPU_ID_TPC_QMAN_ARC20, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_2_2] = CPU_ID_TPC_QMAN_ARC20, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_2_3] = CPU_ID_TPC_QMAN_ARC20, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_3_0] = CPU_ID_TPC_QMAN_ARC21, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_3_1] = CPU_ID_TPC_QMAN_ARC21, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_3_2] = CPU_ID_TPC_QMAN_ARC21, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_3_3] = CPU_ID_TPC_QMAN_ARC21, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_4_0] = CPU_ID_TPC_QMAN_ARC22, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_4_1] = CPU_ID_TPC_QMAN_ARC22, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_4_2] = CPU_ID_TPC_QMAN_ARC22, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_4_3] = CPU_ID_TPC_QMAN_ARC22, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_5_0] = CPU_ID_TPC_QMAN_ARC23, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_5_1] = CPU_ID_TPC_QMAN_ARC23, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_5_2] = CPU_ID_TPC_QMAN_ARC23, |
| [GAUDI2_QUEUE_ID_DCORE3_TPC_5_3] = CPU_ID_TPC_QMAN_ARC23, |
| [GAUDI2_QUEUE_ID_NIC_0_0] = CPU_ID_NIC_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_NIC_0_1] = CPU_ID_NIC_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_NIC_0_2] = CPU_ID_NIC_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_NIC_0_3] = CPU_ID_NIC_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_NIC_1_0] = CPU_ID_NIC_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_NIC_1_1] = CPU_ID_NIC_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_NIC_1_2] = CPU_ID_NIC_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_NIC_1_3] = CPU_ID_NIC_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_NIC_2_0] = CPU_ID_NIC_QMAN_ARC2, |
| [GAUDI2_QUEUE_ID_NIC_2_1] = CPU_ID_NIC_QMAN_ARC2, |
| [GAUDI2_QUEUE_ID_NIC_2_2] = CPU_ID_NIC_QMAN_ARC2, |
| [GAUDI2_QUEUE_ID_NIC_2_3] = CPU_ID_NIC_QMAN_ARC2, |
| [GAUDI2_QUEUE_ID_NIC_3_0] = CPU_ID_NIC_QMAN_ARC3, |
| [GAUDI2_QUEUE_ID_NIC_3_1] = CPU_ID_NIC_QMAN_ARC3, |
| [GAUDI2_QUEUE_ID_NIC_3_2] = CPU_ID_NIC_QMAN_ARC3, |
| [GAUDI2_QUEUE_ID_NIC_3_3] = CPU_ID_NIC_QMAN_ARC3, |
| [GAUDI2_QUEUE_ID_NIC_4_0] = CPU_ID_NIC_QMAN_ARC4, |
| [GAUDI2_QUEUE_ID_NIC_4_1] = CPU_ID_NIC_QMAN_ARC4, |
| [GAUDI2_QUEUE_ID_NIC_4_2] = CPU_ID_NIC_QMAN_ARC4, |
| [GAUDI2_QUEUE_ID_NIC_4_3] = CPU_ID_NIC_QMAN_ARC4, |
| [GAUDI2_QUEUE_ID_NIC_5_0] = CPU_ID_NIC_QMAN_ARC5, |
| [GAUDI2_QUEUE_ID_NIC_5_1] = CPU_ID_NIC_QMAN_ARC5, |
| [GAUDI2_QUEUE_ID_NIC_5_2] = CPU_ID_NIC_QMAN_ARC5, |
| [GAUDI2_QUEUE_ID_NIC_5_3] = CPU_ID_NIC_QMAN_ARC5, |
| [GAUDI2_QUEUE_ID_NIC_6_0] = CPU_ID_NIC_QMAN_ARC6, |
| [GAUDI2_QUEUE_ID_NIC_6_1] = CPU_ID_NIC_QMAN_ARC6, |
| [GAUDI2_QUEUE_ID_NIC_6_2] = CPU_ID_NIC_QMAN_ARC6, |
| [GAUDI2_QUEUE_ID_NIC_6_3] = CPU_ID_NIC_QMAN_ARC6, |
| [GAUDI2_QUEUE_ID_NIC_7_0] = CPU_ID_NIC_QMAN_ARC7, |
| [GAUDI2_QUEUE_ID_NIC_7_1] = CPU_ID_NIC_QMAN_ARC7, |
| [GAUDI2_QUEUE_ID_NIC_7_2] = CPU_ID_NIC_QMAN_ARC7, |
| [GAUDI2_QUEUE_ID_NIC_7_3] = CPU_ID_NIC_QMAN_ARC7, |
| [GAUDI2_QUEUE_ID_NIC_8_0] = CPU_ID_NIC_QMAN_ARC8, |
| [GAUDI2_QUEUE_ID_NIC_8_1] = CPU_ID_NIC_QMAN_ARC8, |
| [GAUDI2_QUEUE_ID_NIC_8_2] = CPU_ID_NIC_QMAN_ARC8, |
| [GAUDI2_QUEUE_ID_NIC_8_3] = CPU_ID_NIC_QMAN_ARC8, |
| [GAUDI2_QUEUE_ID_NIC_9_0] = CPU_ID_NIC_QMAN_ARC9, |
| [GAUDI2_QUEUE_ID_NIC_9_1] = CPU_ID_NIC_QMAN_ARC9, |
| [GAUDI2_QUEUE_ID_NIC_9_2] = CPU_ID_NIC_QMAN_ARC9, |
| [GAUDI2_QUEUE_ID_NIC_9_3] = CPU_ID_NIC_QMAN_ARC9, |
| [GAUDI2_QUEUE_ID_NIC_10_0] = CPU_ID_NIC_QMAN_ARC10, |
| [GAUDI2_QUEUE_ID_NIC_10_1] = CPU_ID_NIC_QMAN_ARC10, |
| [GAUDI2_QUEUE_ID_NIC_10_2] = CPU_ID_NIC_QMAN_ARC10, |
| [GAUDI2_QUEUE_ID_NIC_10_3] = CPU_ID_NIC_QMAN_ARC10, |
| [GAUDI2_QUEUE_ID_NIC_11_0] = CPU_ID_NIC_QMAN_ARC11, |
| [GAUDI2_QUEUE_ID_NIC_11_1] = CPU_ID_NIC_QMAN_ARC11, |
| [GAUDI2_QUEUE_ID_NIC_11_2] = CPU_ID_NIC_QMAN_ARC11, |
| [GAUDI2_QUEUE_ID_NIC_11_3] = CPU_ID_NIC_QMAN_ARC11, |
| [GAUDI2_QUEUE_ID_NIC_12_0] = CPU_ID_NIC_QMAN_ARC12, |
| [GAUDI2_QUEUE_ID_NIC_12_1] = CPU_ID_NIC_QMAN_ARC12, |
| [GAUDI2_QUEUE_ID_NIC_12_2] = CPU_ID_NIC_QMAN_ARC12, |
| [GAUDI2_QUEUE_ID_NIC_12_3] = CPU_ID_NIC_QMAN_ARC12, |
| [GAUDI2_QUEUE_ID_NIC_13_0] = CPU_ID_NIC_QMAN_ARC13, |
| [GAUDI2_QUEUE_ID_NIC_13_1] = CPU_ID_NIC_QMAN_ARC13, |
| [GAUDI2_QUEUE_ID_NIC_13_2] = CPU_ID_NIC_QMAN_ARC13, |
| [GAUDI2_QUEUE_ID_NIC_13_3] = CPU_ID_NIC_QMAN_ARC13, |
| [GAUDI2_QUEUE_ID_NIC_14_0] = CPU_ID_NIC_QMAN_ARC14, |
| [GAUDI2_QUEUE_ID_NIC_14_1] = CPU_ID_NIC_QMAN_ARC14, |
| [GAUDI2_QUEUE_ID_NIC_14_2] = CPU_ID_NIC_QMAN_ARC14, |
| [GAUDI2_QUEUE_ID_NIC_14_3] = CPU_ID_NIC_QMAN_ARC14, |
| [GAUDI2_QUEUE_ID_NIC_15_0] = CPU_ID_NIC_QMAN_ARC15, |
| [GAUDI2_QUEUE_ID_NIC_15_1] = CPU_ID_NIC_QMAN_ARC15, |
| [GAUDI2_QUEUE_ID_NIC_15_2] = CPU_ID_NIC_QMAN_ARC15, |
| [GAUDI2_QUEUE_ID_NIC_15_3] = CPU_ID_NIC_QMAN_ARC15, |
| [GAUDI2_QUEUE_ID_NIC_16_0] = CPU_ID_NIC_QMAN_ARC16, |
| [GAUDI2_QUEUE_ID_NIC_16_1] = CPU_ID_NIC_QMAN_ARC16, |
| [GAUDI2_QUEUE_ID_NIC_16_2] = CPU_ID_NIC_QMAN_ARC16, |
| [GAUDI2_QUEUE_ID_NIC_16_3] = CPU_ID_NIC_QMAN_ARC16, |
| [GAUDI2_QUEUE_ID_NIC_17_0] = CPU_ID_NIC_QMAN_ARC17, |
| [GAUDI2_QUEUE_ID_NIC_17_1] = CPU_ID_NIC_QMAN_ARC17, |
| [GAUDI2_QUEUE_ID_NIC_17_2] = CPU_ID_NIC_QMAN_ARC17, |
| [GAUDI2_QUEUE_ID_NIC_17_3] = CPU_ID_NIC_QMAN_ARC17, |
| [GAUDI2_QUEUE_ID_NIC_18_0] = CPU_ID_NIC_QMAN_ARC18, |
| [GAUDI2_QUEUE_ID_NIC_18_1] = CPU_ID_NIC_QMAN_ARC18, |
| [GAUDI2_QUEUE_ID_NIC_18_2] = CPU_ID_NIC_QMAN_ARC18, |
| [GAUDI2_QUEUE_ID_NIC_18_3] = CPU_ID_NIC_QMAN_ARC18, |
| [GAUDI2_QUEUE_ID_NIC_19_0] = CPU_ID_NIC_QMAN_ARC19, |
| [GAUDI2_QUEUE_ID_NIC_19_1] = CPU_ID_NIC_QMAN_ARC19, |
| [GAUDI2_QUEUE_ID_NIC_19_2] = CPU_ID_NIC_QMAN_ARC19, |
| [GAUDI2_QUEUE_ID_NIC_19_3] = CPU_ID_NIC_QMAN_ARC19, |
| [GAUDI2_QUEUE_ID_NIC_20_0] = CPU_ID_NIC_QMAN_ARC20, |
| [GAUDI2_QUEUE_ID_NIC_20_1] = CPU_ID_NIC_QMAN_ARC20, |
| [GAUDI2_QUEUE_ID_NIC_20_2] = CPU_ID_NIC_QMAN_ARC20, |
| [GAUDI2_QUEUE_ID_NIC_20_3] = CPU_ID_NIC_QMAN_ARC20, |
| [GAUDI2_QUEUE_ID_NIC_21_0] = CPU_ID_NIC_QMAN_ARC21, |
| [GAUDI2_QUEUE_ID_NIC_21_1] = CPU_ID_NIC_QMAN_ARC21, |
| [GAUDI2_QUEUE_ID_NIC_21_2] = CPU_ID_NIC_QMAN_ARC21, |
| [GAUDI2_QUEUE_ID_NIC_21_3] = CPU_ID_NIC_QMAN_ARC21, |
| [GAUDI2_QUEUE_ID_NIC_22_0] = CPU_ID_NIC_QMAN_ARC22, |
| [GAUDI2_QUEUE_ID_NIC_22_1] = CPU_ID_NIC_QMAN_ARC22, |
| [GAUDI2_QUEUE_ID_NIC_22_2] = CPU_ID_NIC_QMAN_ARC22, |
| [GAUDI2_QUEUE_ID_NIC_22_3] = CPU_ID_NIC_QMAN_ARC22, |
| [GAUDI2_QUEUE_ID_NIC_23_0] = CPU_ID_NIC_QMAN_ARC23, |
| [GAUDI2_QUEUE_ID_NIC_23_1] = CPU_ID_NIC_QMAN_ARC23, |
| [GAUDI2_QUEUE_ID_NIC_23_2] = CPU_ID_NIC_QMAN_ARC23, |
| [GAUDI2_QUEUE_ID_NIC_23_3] = CPU_ID_NIC_QMAN_ARC23, |
| [GAUDI2_QUEUE_ID_ROT_0_0] = CPU_ID_ROT_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_ROT_0_1] = CPU_ID_ROT_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_ROT_0_2] = CPU_ID_ROT_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_ROT_0_3] = CPU_ID_ROT_QMAN_ARC0, |
| [GAUDI2_QUEUE_ID_ROT_1_0] = CPU_ID_ROT_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_ROT_1_1] = CPU_ID_ROT_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_ROT_1_2] = CPU_ID_ROT_QMAN_ARC1, |
| [GAUDI2_QUEUE_ID_ROT_1_3] = CPU_ID_ROT_QMAN_ARC1 |
| }; |
| |
| const u32 gaudi2_dma_core_blocks_bases[DMA_CORE_ID_SIZE] = { |
| [DMA_CORE_ID_PDMA0] = mmPDMA0_CORE_BASE, |
| [DMA_CORE_ID_PDMA1] = mmPDMA1_CORE_BASE, |
| [DMA_CORE_ID_EDMA0] = mmDCORE0_EDMA0_CORE_BASE, |
| [DMA_CORE_ID_EDMA1] = mmDCORE0_EDMA1_CORE_BASE, |
| [DMA_CORE_ID_EDMA2] = mmDCORE1_EDMA0_CORE_BASE, |
| [DMA_CORE_ID_EDMA3] = mmDCORE1_EDMA1_CORE_BASE, |
| [DMA_CORE_ID_EDMA4] = mmDCORE2_EDMA0_CORE_BASE, |
| [DMA_CORE_ID_EDMA5] = mmDCORE2_EDMA1_CORE_BASE, |
| [DMA_CORE_ID_EDMA6] = mmDCORE3_EDMA0_CORE_BASE, |
| [DMA_CORE_ID_EDMA7] = mmDCORE3_EDMA1_CORE_BASE, |
| [DMA_CORE_ID_KDMA] = mmARC_FARM_KDMA_BASE |
| }; |
| |
| const u32 gaudi2_mme_acc_blocks_bases[MME_ID_SIZE] = { |
| [MME_ID_DCORE0] = mmDCORE0_MME_ACC_BASE, |
| [MME_ID_DCORE1] = mmDCORE1_MME_ACC_BASE, |
| [MME_ID_DCORE2] = mmDCORE2_MME_ACC_BASE, |
| [MME_ID_DCORE3] = mmDCORE3_MME_ACC_BASE |
| }; |
| |
| static const u32 gaudi2_tpc_cfg_blocks_bases[TPC_ID_SIZE] = { |
| [TPC_ID_DCORE0_TPC0] = mmDCORE0_TPC0_CFG_BASE, |
| [TPC_ID_DCORE0_TPC1] = mmDCORE0_TPC1_CFG_BASE, |
| [TPC_ID_DCORE0_TPC2] = mmDCORE0_TPC2_CFG_BASE, |
| [TPC_ID_DCORE0_TPC3] = mmDCORE0_TPC3_CFG_BASE, |
| [TPC_ID_DCORE0_TPC4] = mmDCORE0_TPC4_CFG_BASE, |
| [TPC_ID_DCORE0_TPC5] = mmDCORE0_TPC5_CFG_BASE, |
| [TPC_ID_DCORE1_TPC0] = mmDCORE1_TPC0_CFG_BASE, |
| [TPC_ID_DCORE1_TPC1] = mmDCORE1_TPC1_CFG_BASE, |
| [TPC_ID_DCORE1_TPC2] = mmDCORE1_TPC2_CFG_BASE, |
| [TPC_ID_DCORE1_TPC3] = mmDCORE1_TPC3_CFG_BASE, |
| [TPC_ID_DCORE1_TPC4] = mmDCORE1_TPC4_CFG_BASE, |
| [TPC_ID_DCORE1_TPC5] = mmDCORE1_TPC5_CFG_BASE, |
| [TPC_ID_DCORE2_TPC0] = mmDCORE2_TPC0_CFG_BASE, |
| [TPC_ID_DCORE2_TPC1] = mmDCORE2_TPC1_CFG_BASE, |
| [TPC_ID_DCORE2_TPC2] = mmDCORE2_TPC2_CFG_BASE, |
| [TPC_ID_DCORE2_TPC3] = mmDCORE2_TPC3_CFG_BASE, |
| [TPC_ID_DCORE2_TPC4] = mmDCORE2_TPC4_CFG_BASE, |
| [TPC_ID_DCORE2_TPC5] = mmDCORE2_TPC5_CFG_BASE, |
| [TPC_ID_DCORE3_TPC0] = mmDCORE3_TPC0_CFG_BASE, |
| [TPC_ID_DCORE3_TPC1] = mmDCORE3_TPC1_CFG_BASE, |
| [TPC_ID_DCORE3_TPC2] = mmDCORE3_TPC2_CFG_BASE, |
| [TPC_ID_DCORE3_TPC3] = mmDCORE3_TPC3_CFG_BASE, |
| [TPC_ID_DCORE3_TPC4] = mmDCORE3_TPC4_CFG_BASE, |
| [TPC_ID_DCORE3_TPC5] = mmDCORE3_TPC5_CFG_BASE, |
| [TPC_ID_DCORE0_TPC6] = mmDCORE0_TPC6_CFG_BASE, |
| }; |
| |
| static const u32 gaudi2_tpc_eml_cfg_blocks_bases[TPC_ID_SIZE] = { |
| [TPC_ID_DCORE0_TPC0] = mmDCORE0_TPC0_EML_CFG_BASE, |
| [TPC_ID_DCORE0_TPC1] = mmDCORE0_TPC1_EML_CFG_BASE, |
| [TPC_ID_DCORE0_TPC2] = mmDCORE0_TPC2_EML_CFG_BASE, |
| [TPC_ID_DCORE0_TPC3] = mmDCORE0_TPC3_EML_CFG_BASE, |
| [TPC_ID_DCORE0_TPC4] = mmDCORE0_TPC4_EML_CFG_BASE, |
| [TPC_ID_DCORE0_TPC5] = mmDCORE0_TPC5_EML_CFG_BASE, |
| [TPC_ID_DCORE1_TPC0] = mmDCORE1_TPC0_EML_CFG_BASE, |
| [TPC_ID_DCORE1_TPC1] = mmDCORE1_TPC1_EML_CFG_BASE, |
| [TPC_ID_DCORE1_TPC2] = mmDCORE1_TPC2_EML_CFG_BASE, |
| [TPC_ID_DCORE1_TPC3] = mmDCORE1_TPC3_EML_CFG_BASE, |
| [TPC_ID_DCORE1_TPC4] = mmDCORE1_TPC4_EML_CFG_BASE, |
| [TPC_ID_DCORE1_TPC5] = mmDCORE1_TPC5_EML_CFG_BASE, |
| [TPC_ID_DCORE2_TPC0] = mmDCORE2_TPC0_EML_CFG_BASE, |
| [TPC_ID_DCORE2_TPC1] = mmDCORE2_TPC1_EML_CFG_BASE, |
| [TPC_ID_DCORE2_TPC2] = mmDCORE2_TPC2_EML_CFG_BASE, |
| [TPC_ID_DCORE2_TPC3] = mmDCORE2_TPC3_EML_CFG_BASE, |
| [TPC_ID_DCORE2_TPC4] = mmDCORE2_TPC4_EML_CFG_BASE, |
| [TPC_ID_DCORE2_TPC5] = mmDCORE2_TPC5_EML_CFG_BASE, |
| [TPC_ID_DCORE3_TPC0] = mmDCORE3_TPC0_EML_CFG_BASE, |
| [TPC_ID_DCORE3_TPC1] = mmDCORE3_TPC1_EML_CFG_BASE, |
| [TPC_ID_DCORE3_TPC2] = mmDCORE3_TPC2_EML_CFG_BASE, |
| [TPC_ID_DCORE3_TPC3] = mmDCORE3_TPC3_EML_CFG_BASE, |
| [TPC_ID_DCORE3_TPC4] = mmDCORE3_TPC4_EML_CFG_BASE, |
| [TPC_ID_DCORE3_TPC5] = mmDCORE3_TPC5_EML_CFG_BASE, |
| [TPC_ID_DCORE0_TPC6] = mmDCORE0_TPC6_EML_CFG_BASE, |
| }; |
| |
| const u32 gaudi2_rot_blocks_bases[ROTATOR_ID_SIZE] = { |
| [ROTATOR_ID_0] = mmROT0_BASE, |
| [ROTATOR_ID_1] = mmROT1_BASE |
| }; |
| |
| static const u32 gaudi2_tpc_id_to_queue_id[TPC_ID_SIZE] = { |
| [TPC_ID_DCORE0_TPC0] = GAUDI2_QUEUE_ID_DCORE0_TPC_0_0, |
| [TPC_ID_DCORE0_TPC1] = GAUDI2_QUEUE_ID_DCORE0_TPC_1_0, |
| [TPC_ID_DCORE0_TPC2] = GAUDI2_QUEUE_ID_DCORE0_TPC_2_0, |
| [TPC_ID_DCORE0_TPC3] = GAUDI2_QUEUE_ID_DCORE0_TPC_3_0, |
| [TPC_ID_DCORE0_TPC4] = GAUDI2_QUEUE_ID_DCORE0_TPC_4_0, |
| [TPC_ID_DCORE0_TPC5] = GAUDI2_QUEUE_ID_DCORE0_TPC_5_0, |
| [TPC_ID_DCORE1_TPC0] = GAUDI2_QUEUE_ID_DCORE1_TPC_0_0, |
| [TPC_ID_DCORE1_TPC1] = GAUDI2_QUEUE_ID_DCORE1_TPC_1_0, |
| [TPC_ID_DCORE1_TPC2] = GAUDI2_QUEUE_ID_DCORE1_TPC_2_0, |
| [TPC_ID_DCORE1_TPC3] = GAUDI2_QUEUE_ID_DCORE1_TPC_3_0, |
| [TPC_ID_DCORE1_TPC4] = GAUDI2_QUEUE_ID_DCORE1_TPC_4_0, |
| [TPC_ID_DCORE1_TPC5] = GAUDI2_QUEUE_ID_DCORE1_TPC_5_0, |
| [TPC_ID_DCORE2_TPC0] = GAUDI2_QUEUE_ID_DCORE2_TPC_0_0, |
| [TPC_ID_DCORE2_TPC1] = GAUDI2_QUEUE_ID_DCORE2_TPC_1_0, |
| [TPC_ID_DCORE2_TPC2] = GAUDI2_QUEUE_ID_DCORE2_TPC_2_0, |
| [TPC_ID_DCORE2_TPC3] = GAUDI2_QUEUE_ID_DCORE2_TPC_3_0, |
| [TPC_ID_DCORE2_TPC4] = GAUDI2_QUEUE_ID_DCORE2_TPC_4_0, |
| [TPC_ID_DCORE2_TPC5] = GAUDI2_QUEUE_ID_DCORE2_TPC_5_0, |
| [TPC_ID_DCORE3_TPC0] = GAUDI2_QUEUE_ID_DCORE3_TPC_0_0, |
| [TPC_ID_DCORE3_TPC1] = GAUDI2_QUEUE_ID_DCORE3_TPC_1_0, |
| [TPC_ID_DCORE3_TPC2] = GAUDI2_QUEUE_ID_DCORE3_TPC_2_0, |
| [TPC_ID_DCORE3_TPC3] = GAUDI2_QUEUE_ID_DCORE3_TPC_3_0, |
| [TPC_ID_DCORE3_TPC4] = GAUDI2_QUEUE_ID_DCORE3_TPC_4_0, |
| [TPC_ID_DCORE3_TPC5] = GAUDI2_QUEUE_ID_DCORE3_TPC_5_0, |
| [TPC_ID_DCORE0_TPC6] = GAUDI2_QUEUE_ID_DCORE0_TPC_6_0, |
| }; |
| |
| static const u32 gaudi2_rot_id_to_queue_id[ROTATOR_ID_SIZE] = { |
| [ROTATOR_ID_0] = GAUDI2_QUEUE_ID_ROT_0_0, |
| [ROTATOR_ID_1] = GAUDI2_QUEUE_ID_ROT_1_0, |
| }; |
| |
| static const u32 gaudi2_tpc_engine_id_to_tpc_id[] = { |
| [GAUDI2_DCORE0_ENGINE_ID_TPC_0] = TPC_ID_DCORE0_TPC0, |
| [GAUDI2_DCORE0_ENGINE_ID_TPC_1] = TPC_ID_DCORE0_TPC1, |
| [GAUDI2_DCORE0_ENGINE_ID_TPC_2] = TPC_ID_DCORE0_TPC2, |
| [GAUDI2_DCORE0_ENGINE_ID_TPC_3] = TPC_ID_DCORE0_TPC3, |
| [GAUDI2_DCORE0_ENGINE_ID_TPC_4] = TPC_ID_DCORE0_TPC4, |
| [GAUDI2_DCORE0_ENGINE_ID_TPC_5] = TPC_ID_DCORE0_TPC5, |
| [GAUDI2_DCORE1_ENGINE_ID_TPC_0] = TPC_ID_DCORE1_TPC0, |
| [GAUDI2_DCORE1_ENGINE_ID_TPC_1] = TPC_ID_DCORE1_TPC1, |
| [GAUDI2_DCORE1_ENGINE_ID_TPC_2] = TPC_ID_DCORE1_TPC2, |
| [GAUDI2_DCORE1_ENGINE_ID_TPC_3] = TPC_ID_DCORE1_TPC3, |
| [GAUDI2_DCORE1_ENGINE_ID_TPC_4] = TPC_ID_DCORE1_TPC4, |
| [GAUDI2_DCORE1_ENGINE_ID_TPC_5] = TPC_ID_DCORE1_TPC5, |
| [GAUDI2_DCORE2_ENGINE_ID_TPC_0] = TPC_ID_DCORE2_TPC0, |
| [GAUDI2_DCORE2_ENGINE_ID_TPC_1] = TPC_ID_DCORE2_TPC1, |
| [GAUDI2_DCORE2_ENGINE_ID_TPC_2] = TPC_ID_DCORE2_TPC2, |
| [GAUDI2_DCORE2_ENGINE_ID_TPC_3] = TPC_ID_DCORE2_TPC3, |
| [GAUDI2_DCORE2_ENGINE_ID_TPC_4] = TPC_ID_DCORE2_TPC4, |
| [GAUDI2_DCORE2_ENGINE_ID_TPC_5] = TPC_ID_DCORE2_TPC5, |
| [GAUDI2_DCORE3_ENGINE_ID_TPC_0] = TPC_ID_DCORE3_TPC0, |
| [GAUDI2_DCORE3_ENGINE_ID_TPC_1] = TPC_ID_DCORE3_TPC1, |
| [GAUDI2_DCORE3_ENGINE_ID_TPC_2] = TPC_ID_DCORE3_TPC2, |
| [GAUDI2_DCORE3_ENGINE_ID_TPC_3] = TPC_ID_DCORE3_TPC3, |
| [GAUDI2_DCORE3_ENGINE_ID_TPC_4] = TPC_ID_DCORE3_TPC4, |
| [GAUDI2_DCORE3_ENGINE_ID_TPC_5] = TPC_ID_DCORE3_TPC5, |
| /* the PCI TPC is placed last (mapped liked HW) */ |
| [GAUDI2_DCORE0_ENGINE_ID_TPC_6] = TPC_ID_DCORE0_TPC6, |
| }; |
| |
| static const u32 gaudi2_mme_engine_id_to_mme_id[] = { |
| [GAUDI2_DCORE0_ENGINE_ID_MME] = MME_ID_DCORE0, |
| [GAUDI2_DCORE1_ENGINE_ID_MME] = MME_ID_DCORE1, |
| [GAUDI2_DCORE2_ENGINE_ID_MME] = MME_ID_DCORE2, |
| [GAUDI2_DCORE3_ENGINE_ID_MME] = MME_ID_DCORE3, |
| }; |
| |
| static const u32 gaudi2_edma_engine_id_to_edma_id[] = { |
| [GAUDI2_ENGINE_ID_PDMA_0] = DMA_CORE_ID_PDMA0, |
| [GAUDI2_ENGINE_ID_PDMA_1] = DMA_CORE_ID_PDMA1, |
| [GAUDI2_DCORE0_ENGINE_ID_EDMA_0] = DMA_CORE_ID_EDMA0, |
| [GAUDI2_DCORE0_ENGINE_ID_EDMA_1] = DMA_CORE_ID_EDMA1, |
| [GAUDI2_DCORE1_ENGINE_ID_EDMA_0] = DMA_CORE_ID_EDMA2, |
| [GAUDI2_DCORE1_ENGINE_ID_EDMA_1] = DMA_CORE_ID_EDMA3, |
| [GAUDI2_DCORE2_ENGINE_ID_EDMA_0] = DMA_CORE_ID_EDMA4, |
| [GAUDI2_DCORE2_ENGINE_ID_EDMA_1] = DMA_CORE_ID_EDMA5, |
| [GAUDI2_DCORE3_ENGINE_ID_EDMA_0] = DMA_CORE_ID_EDMA6, |
| [GAUDI2_DCORE3_ENGINE_ID_EDMA_1] = DMA_CORE_ID_EDMA7, |
| [GAUDI2_ENGINE_ID_KDMA] = DMA_CORE_ID_KDMA, |
| }; |
| |
| const u32 edma_stream_base[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES] = { |
| GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0, |
| GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0, |
| GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0, |
| GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0, |
| GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0, |
| GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0, |
| GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0, |
| GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0, |
| }; |
| |
| static const char gaudi2_vdec_irq_name[GAUDI2_VDEC_MSIX_ENTRIES][GAUDI2_MAX_STRING_LEN] = { |
| "gaudi2 vdec 0_0", "gaudi2 vdec 0_0 abnormal", |
| "gaudi2 vdec 0_1", "gaudi2 vdec 0_1 abnormal", |
| "gaudi2 vdec 1_0", "gaudi2 vdec 1_0 abnormal", |
| "gaudi2 vdec 1_1", "gaudi2 vdec 1_1 abnormal", |
| "gaudi2 vdec 2_0", "gaudi2 vdec 2_0 abnormal", |
| "gaudi2 vdec 2_1", "gaudi2 vdec 2_1 abnormal", |
| "gaudi2 vdec 3_0", "gaudi2 vdec 3_0 abnormal", |
| "gaudi2 vdec 3_1", "gaudi2 vdec 3_1 abnormal", |
| "gaudi2 vdec s_0", "gaudi2 vdec s_0 abnormal", |
| "gaudi2 vdec s_1", "gaudi2 vdec s_1 abnormal" |
| }; |
| |
| enum rtr_id { |
| DCORE0_RTR0, |
| DCORE0_RTR1, |
| DCORE0_RTR2, |
| DCORE0_RTR3, |
| DCORE0_RTR4, |
| DCORE0_RTR5, |
| DCORE0_RTR6, |
| DCORE0_RTR7, |
| DCORE1_RTR0, |
| DCORE1_RTR1, |
| DCORE1_RTR2, |
| DCORE1_RTR3, |
| DCORE1_RTR4, |
| DCORE1_RTR5, |
| DCORE1_RTR6, |
| DCORE1_RTR7, |
| DCORE2_RTR0, |
| DCORE2_RTR1, |
| DCORE2_RTR2, |
| DCORE2_RTR3, |
| DCORE2_RTR4, |
| DCORE2_RTR5, |
| DCORE2_RTR6, |
| DCORE2_RTR7, |
| DCORE3_RTR0, |
| DCORE3_RTR1, |
| DCORE3_RTR2, |
| DCORE3_RTR3, |
| DCORE3_RTR4, |
| DCORE3_RTR5, |
| DCORE3_RTR6, |
| DCORE3_RTR7, |
| }; |
| |
| static const u32 gaudi2_tpc_initiator_hbw_rtr_id[NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES + 1] = { |
| DCORE0_RTR1, DCORE0_RTR1, DCORE0_RTR2, DCORE0_RTR2, DCORE0_RTR3, DCORE0_RTR3, |
| DCORE1_RTR6, DCORE1_RTR6, DCORE1_RTR5, DCORE1_RTR5, DCORE1_RTR4, DCORE1_RTR4, |
| DCORE2_RTR3, DCORE2_RTR3, DCORE2_RTR2, DCORE2_RTR2, DCORE2_RTR1, DCORE2_RTR1, |
| DCORE3_RTR4, DCORE3_RTR4, DCORE3_RTR5, DCORE3_RTR5, DCORE3_RTR6, DCORE3_RTR6, |
| DCORE0_RTR0 |
| }; |
| |
| static const u32 gaudi2_tpc_initiator_lbw_rtr_id[NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES + 1] = { |
| DCORE0_RTR1, DCORE0_RTR1, DCORE0_RTR1, DCORE0_RTR1, DCORE0_RTR2, DCORE0_RTR2, |
| DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR6, DCORE1_RTR6, DCORE1_RTR5, DCORE1_RTR5, |
| DCORE2_RTR2, DCORE2_RTR2, DCORE2_RTR1, DCORE2_RTR1, DCORE2_RTR0, DCORE2_RTR0, |
| DCORE3_RTR5, DCORE3_RTR5, DCORE3_RTR6, DCORE3_RTR6, DCORE3_RTR7, DCORE3_RTR7, |
| DCORE0_RTR0 |
| }; |
| |
| static const u32 gaudi2_dec_initiator_hbw_rtr_id[NUMBER_OF_DEC] = { |
| DCORE0_RTR0, DCORE0_RTR0, DCORE1_RTR7, DCORE1_RTR7, DCORE2_RTR0, DCORE2_RTR0, |
| DCORE3_RTR7, DCORE3_RTR7, DCORE0_RTR0, DCORE0_RTR0 |
| }; |
| |
| static const u32 gaudi2_dec_initiator_lbw_rtr_id[NUMBER_OF_DEC] = { |
| DCORE0_RTR1, DCORE0_RTR1, DCORE1_RTR6, DCORE1_RTR6, DCORE2_RTR1, DCORE2_RTR1, |
| DCORE3_RTR6, DCORE3_RTR6, DCORE0_RTR0, DCORE0_RTR0 |
| }; |
| |
| static const u32 gaudi2_nic_initiator_hbw_rtr_id[NIC_NUMBER_OF_MACROS] = { |
| DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE2_RTR0, |
| DCORE2_RTR0, DCORE2_RTR0, DCORE2_RTR0, DCORE3_RTR7, DCORE3_RTR7, DCORE3_RTR7 |
| }; |
| |
| static const u32 gaudi2_nic_initiator_lbw_rtr_id[NIC_NUMBER_OF_MACROS] = { |
| DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE2_RTR0, |
| DCORE2_RTR0, DCORE2_RTR0, DCORE2_RTR0, DCORE3_RTR7, DCORE3_RTR7, DCORE3_RTR7 |
| }; |
| |
| static const u32 gaudi2_edma_initiator_hbw_sft[NUM_OF_EDMA_PER_DCORE * NUM_OF_DCORES] = { |
| mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE, |
| mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE, |
| mmSFT1_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE, |
| mmSFT1_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE, |
| mmSFT2_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE, |
| mmSFT2_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE, |
| mmSFT3_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE, |
| mmSFT3_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE |
| }; |
| |
| static const u32 gaudi2_pdma_initiator_hbw_rtr_id[NUM_OF_PDMA] = { |
| DCORE0_RTR0, DCORE0_RTR0 |
| }; |
| |
| static const u32 gaudi2_pdma_initiator_lbw_rtr_id[NUM_OF_PDMA] = { |
| DCORE0_RTR2, DCORE0_RTR2 |
| }; |
| |
| static const u32 gaudi2_rot_initiator_hbw_rtr_id[NUM_OF_ROT] = { |
| DCORE2_RTR0, DCORE3_RTR7 |
| }; |
| |
| static const u32 gaudi2_rot_initiator_lbw_rtr_id[NUM_OF_ROT] = { |
| DCORE2_RTR2, DCORE3_RTR5 |
| }; |
| |
| struct mme_initiators_rtr_id { |
| u32 wap0; |
| u32 wap1; |
| u32 write; |
| u32 read; |
| u32 sbte0; |
| u32 sbte1; |
| u32 sbte2; |
| u32 sbte3; |
| u32 sbte4; |
| }; |
| |
| enum mme_initiators { |
| MME_WAP0 = 0, |
| MME_WAP1, |
| MME_WRITE, |
| MME_READ, |
| MME_SBTE0, |
| MME_SBTE1, |
| MME_SBTE2, |
| MME_SBTE3, |
| MME_SBTE4, |
| MME_INITIATORS_MAX |
| }; |
| |
| static const struct mme_initiators_rtr_id |
| gaudi2_mme_initiator_rtr_id[NUM_OF_MME_PER_DCORE * NUM_OF_DCORES] = { |
| { .wap0 = 5, .wap1 = 7, .write = 6, .read = 7, |
| .sbte0 = 7, .sbte1 = 4, .sbte2 = 4, .sbte3 = 5, .sbte4 = 6}, |
| { .wap0 = 10, .wap1 = 8, .write = 9, .read = 8, |
| .sbte0 = 11, .sbte1 = 11, .sbte2 = 10, .sbte3 = 9, .sbte4 = 8}, |
| { .wap0 = 21, .wap1 = 23, .write = 22, .read = 23, |
| .sbte0 = 20, .sbte1 = 20, .sbte2 = 21, .sbte3 = 22, .sbte4 = 23}, |
| { .wap0 = 30, .wap1 = 28, .write = 29, .read = 30, |
| .sbte0 = 31, .sbte1 = 31, .sbte2 = 30, .sbte3 = 29, .sbte4 = 28}, |
| }; |
| |
| enum razwi_event_sources { |
| RAZWI_TPC, |
| RAZWI_MME, |
| RAZWI_EDMA, |
| RAZWI_PDMA, |
| RAZWI_NIC, |
| RAZWI_DEC, |
| RAZWI_ROT, |
| RAZWI_ARC_FARM |
| }; |
| |
| struct hbm_mc_error_causes { |
| u32 mask; |
| char cause[50]; |
| }; |
| |
| static struct hl_special_block_info gaudi2_special_blocks[] = GAUDI2_SPECIAL_BLOCKS; |
| |
| /* Special blocks iterator is currently used to configure security protection bits, |
| * and read global errors. Most HW blocks are addressable and those who aren't (N/A)- |
| * must be skipped. Following configurations are commonly used for both PB config |
| * and global error reading, since currently they both share the same settings. |
| * Once it changes, we must remember to use separate configurations for either one. |
| */ |
| static int gaudi2_iterator_skip_block_types[] = { |
| GAUDI2_BLOCK_TYPE_PLL, |
| GAUDI2_BLOCK_TYPE_EU_BIST, |
| GAUDI2_BLOCK_TYPE_HBM, |
| GAUDI2_BLOCK_TYPE_XFT |
| }; |
| |
| static struct range gaudi2_iterator_skip_block_ranges[] = { |
| /* Skip all PSOC blocks except for PSOC_GLOBAL_CONF */ |
| {mmPSOC_I2C_M0_BASE, mmPSOC_EFUSE_BASE}, |
| {mmPSOC_BTL_BASE, mmPSOC_MSTR_IF_RR_SHRD_HBW_BASE}, |
| /* Skip all CPU blocks except for CPU_IF */ |
| {mmCPU_CA53_CFG_BASE, mmCPU_CA53_CFG_BASE}, |
| {mmCPU_TIMESTAMP_BASE, mmCPU_MSTR_IF_RR_SHRD_HBW_BASE} |
| }; |
| |
| static struct hbm_mc_error_causes hbm_mc_spi[GAUDI2_NUM_OF_HBM_MC_SPI_CAUSE] = { |
| {HBM_MC_SPI_TEMP_PIN_CHG_MASK, "temperature pins changed"}, |
| {HBM_MC_SPI_THR_ENG_MASK, "temperature-based throttling engaged"}, |
| {HBM_MC_SPI_THR_DIS_ENG_MASK, "temperature-based throttling disengaged"}, |
| {HBM_MC_SPI_IEEE1500_COMP_MASK, "IEEE1500 op comp"}, |
| {HBM_MC_SPI_IEEE1500_PAUSED_MASK, "IEEE1500 op paused"}, |
| }; |
| |
| static const char * const hbm_mc_sei_cause[GAUDI2_NUM_OF_HBM_SEI_CAUSE] = { |
| [HBM_SEI_CMD_PARITY_EVEN] = "SEI C/A parity even", |
| [HBM_SEI_CMD_PARITY_ODD] = "SEI C/A parity odd", |
| [HBM_SEI_READ_ERR] = "SEI read data error", |
| [HBM_SEI_WRITE_DATA_PARITY_ERR] = "SEI write data parity error", |
| [HBM_SEI_CATTRIP] = "SEI CATTRIP asserted", |
| [HBM_SEI_MEM_BIST_FAIL] = "SEI memory BIST fail", |
| [HBM_SEI_DFI] = "SEI DFI error", |
| [HBM_SEI_INV_TEMP_READ_OUT] = "SEI invalid temp read", |
| [HBM_SEI_BIST_FAIL] = "SEI BIST fail" |
| }; |
| |
| struct mmu_spi_sei_cause { |
| char cause[50]; |
| int clear_bit; |
| }; |
| |
| static const struct mmu_spi_sei_cause gaudi2_mmu_spi_sei[GAUDI2_NUM_OF_MMU_SPI_SEI_CAUSE] = { |
| {"page fault", 1}, /* INTERRUPT_CLR[1] */ |
| {"page access", 1}, /* INTERRUPT_CLR[1] */ |
| {"bypass ddr", 2}, /* INTERRUPT_CLR[2] */ |
| {"multi hit", 2}, /* INTERRUPT_CLR[2] */ |
| {"mmu rei0", -1}, /* no clear register bit */ |
| {"mmu rei1", -1}, /* no clear register bit */ |
| {"stlb rei0", -1}, /* no clear register bit */ |
| {"stlb rei1", -1}, /* no clear register bit */ |
| {"rr privileged write hit", 2}, /* INTERRUPT_CLR[2] */ |
| {"rr privileged read hit", 2}, /* INTERRUPT_CLR[2] */ |
| {"rr secure write hit", 2}, /* INTERRUPT_CLR[2] */ |
| {"rr secure read hit", 2}, /* INTERRUPT_CLR[2] */ |
| {"bist_fail no use", 2}, /* INTERRUPT_CLR[2] */ |
| {"bist_fail no use", 2}, /* INTERRUPT_CLR[2] */ |
| {"bist_fail no use", 2}, /* INTERRUPT_CLR[2] */ |
| {"bist_fail no use", 2}, /* INTERRUPT_CLR[2] */ |
| {"slave error", 16}, /* INTERRUPT_CLR[16] */ |
| {"dec error", 17}, /* INTERRUPT_CLR[17] */ |
| {"burst fifo full", 2} /* INTERRUPT_CLR[2] */ |
| }; |
| |
| struct gaudi2_cache_invld_params { |
| u64 start_va; |
| u64 end_va; |
| u32 inv_start_val; |
| u32 flags; |
| bool range_invalidation; |
| }; |
| |
| struct gaudi2_tpc_idle_data { |
| struct engines_data *e; |
| unsigned long *mask; |
| bool *is_idle; |
| const char *tpc_fmt; |
| }; |
| |
| struct gaudi2_tpc_mmu_data { |
| u32 rw_asid; |
| }; |
| |
| static s64 gaudi2_state_dump_specs_props[SP_MAX] = {0}; |
| |
| static int gaudi2_memset_device_memory(struct hl_device *hdev, u64 addr, u64 size, u64 val); |
| static bool gaudi2_is_queue_enabled(struct hl_device *hdev, u32 hw_queue_id); |
| static bool gaudi2_is_arc_enabled(struct hl_device *hdev, u64 arc_id); |
| static void gaudi2_clr_arc_id_cap(struct hl_device *hdev, u64 arc_id); |
| static void gaudi2_set_arc_id_cap(struct hl_device *hdev, u64 arc_id); |
| static void gaudi2_memset_device_lbw(struct hl_device *hdev, u32 addr, u32 size, u32 val); |
| static int gaudi2_send_job_to_kdma(struct hl_device *hdev, u64 src_addr, u64 dst_addr, u32 size, |
| bool is_memset); |
| static bool gaudi2_get_tpc_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len, |
| struct engines_data *e); |
| static bool gaudi2_get_mme_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len, |
| struct engines_data *e); |
| static bool gaudi2_get_edma_idle_status(struct hl_device *hdev, u64 *mask_arr, u8 mask_len, |
| struct engines_data *e); |
| static u64 gaudi2_mmu_scramble_addr(struct hl_device *hdev, u64 raw_addr); |
| static u64 gaudi2_mmu_descramble_addr(struct hl_device *hdev, u64 scrambled_addr); |
| |
| static void gaudi2_init_scrambler_hbm(struct hl_device *hdev) |
| { |
| |
| } |
| |
| static u32 gaudi2_get_signal_cb_size(struct hl_device *hdev) |
| { |
| return sizeof(struct packet_msg_short); |
| } |
| |
| static u32 gaudi2_get_wait_cb_size(struct hl_device *hdev) |
| { |
| return sizeof(struct packet_msg_short) * 4 + sizeof(struct packet_fence); |
| } |
| |
| void gaudi2_iterate_tpcs(struct hl_device *hdev, struct iterate_module_ctx *ctx) |
| { |
| struct asic_fixed_properties *prop = &hdev->asic_prop; |
| int dcore, inst, tpc_seq; |
| u32 offset; |
| |
| /* init the return code */ |
| ctx->rc = 0; |
| |
| for (dcore = 0; dcore < NUM_OF_DCORES; dcore++) { |
| for (inst = 0; inst < NUM_OF_TPC_PER_DCORE; inst++) { |
| tpc_seq = dcore * NUM_OF_TPC_PER_DCORE + inst; |
| |
| if (!(prop->tpc_enabled_mask & BIT(tpc_seq))) |
| continue; |
| |
| offset = (DCORE_OFFSET * dcore) + (DCORE_TPC_OFFSET * inst); |
| |
| ctx->fn(hdev, dcore, inst, offset, ctx); |
| if (ctx->rc) { |
| dev_err(hdev->dev, "TPC iterator failed for DCORE%d TPC%d\n", |
| dcore, inst); |
| return; |
| } |
| } |
| } |
| |
| if (!(prop->tpc_enabled_mask & BIT(TPC_ID_DCORE0_TPC6))) |
| return; |
| |
| /* special check for PCI TPC (DCORE0_TPC6) */ |
| offset = DCORE_TPC_OFFSET * (NUM_DCORE0_TPC - 1); |
| ctx->fn(hdev, 0, NUM_DCORE0_TPC - 1, offset, ctx); |
| if (ctx->rc) |
| dev_err(hdev->dev, "TPC iterator failed for DCORE0 TPC6\n"); |
| } |
| |
| static bool gaudi2_host_phys_addr_valid(u64 addr) |
| { |
| if ((addr < HOST_PHYS_BASE_0 + HOST_PHYS_SIZE_0) || (addr >= HOST_PHYS_BASE_1)) |
| return true; |
| |
| return false; |
| } |
| |
| static int set_number_of_functional_hbms(struct hl_device *hdev) |
| { |
| struct asic_fixed_properties *prop = &hdev->asic_prop; |
| u8 faulty_hbms = hweight64(hdev->dram_binning); |
| |
| /* check if all HBMs should be used */ |
| if (!faulty_hbms) { |
| dev_dbg(hdev->dev, "All HBM are in use (no binning)\n"); |
| prop->num_functional_hbms = GAUDI2_HBM_NUM; |
| return 0; |
| } |
| |
| /* |
| * check for error condition in which number of binning |
| * candidates is higher than the maximum supported by the |
| * driver (in which case binning mask shall be ignored and driver will |
| * set the default) |
| */ |
| if (faulty_hbms > MAX_FAULTY_HBMS) { |
| dev_err(hdev->dev, |
| "HBM binning supports max of %d faulty HBMs, supplied mask 0x%llx.\n", |
| MAX_FAULTY_HBMS, hdev->dram_binning); |
| return -EINVAL; |
| } |
| |
| /* |
| * by default, number of functional HBMs in Gaudi2 is always |
| * GAUDI2_HBM_NUM - 1. |
| */ |
| prop->num_functional_hbms = GAUDI2_HBM_NUM - faulty_hbms; |
| return 0; |
| } |
| |
| static bool gaudi2_is_edma_queue_id(u32 queue_id) |
| { |
| |
| switch (queue_id) { |
| case GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3: |
| case GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3: |
| case GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3: |
| case GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3: |
| return true; |
| default: |
| return false; |
| } |
| } |
| |
| static int gaudi2_set_dram_properties(struct hl_device *hdev) |
| { |
| struct asic_fixed_properties *prop = &hdev->asic_prop; |
| u64 hbm_drv_base_offset = 0, edma_pq_base_addr; |
| u32 basic_hbm_page_size, edma_idx = 0; |
| int rc, i; |
| |
| rc = set_number_of_functional_hbms(hdev); |
| if (rc) |
| return -EINVAL; |
| |
| /* |
| * Due to HW bug in which TLB size is x16 smaller than expected we use a workaround |
| * in which we are using x16 bigger page size to be able to populate the entire |
| * HBM mappings in the TLB |
| */ |
| basic_hbm_page_size = prop->num_functional_hbms * SZ_8M; |
| prop->dram_page_size = GAUDI2_COMPENSATE_TLB_PAGE_SIZE_FACTOR * basic_hbm_page_size; |
| prop->device_mem_alloc_default_page_size = prop->dram_page_size; |
| prop->dram_size = prop->num_functional_hbms * SZ_16G; |
| prop->dram_base_address = DRAM_PHYS_BASE; |
| prop->dram_end_address = prop->dram_base_address + prop->dram_size; |
| prop->dram_supports_virtual_memory = true; |
| |
| prop->dram_user_base_address = DRAM_PHYS_BASE + prop->dram_page_size; |
| prop->dram_hints_align_mask = ~GAUDI2_HBM_MMU_SCRM_ADDRESS_MASK; |
| prop->hints_dram_reserved_va_range.start_addr = RESERVED_VA_RANGE_FOR_ARC_ON_HBM_START; |
| prop->hints_dram_reserved_va_range.end_addr = RESERVED_VA_RANGE_FOR_ARC_ON_HBM_END; |
| |
| /* since DRAM page size differs from DMMU page size we need to allocate |
| * DRAM memory in units of dram_page size and mapping this memory in |
| * units of DMMU page size. we overcome this size mismatch using a |
| * scrambling routine which takes a DRAM page and converts it to a DMMU |
| * page. |
| * We therefore: |
| * 1. partition the virtual address space to DRAM-page (whole) pages. |
| * (suppose we get n such pages) |
| * 2. limit the amount of virtual address space we got from 1 above to |
| * a multiple of 64M as we don't want the scrambled address to cross |
| * the DRAM virtual address space. |
| * ( m = (n * DRAM_page_size) / DMMU_page_size). |
| * 3. determine the and address accordingly |
| * end_addr = start_addr + m * 48M |
| * |
| * the DRAM address MSBs (63:48) are not part of the roundup calculation |
| */ |
| prop->dmmu.start_addr = prop->dram_base_address + |
| (prop->dram_page_size * |
| DIV_ROUND_UP_SECTOR_T(prop->dram_size, prop->dram_page_size)); |
| prop->dmmu.end_addr = prop->dmmu.start_addr + prop->dram_page_size * |
| div_u64((VA_HBM_SPACE_END - prop->dmmu.start_addr), prop->dmmu.page_size); |
| /* |
| * Driver can't share an (48MB) HBM page with the F/W in order to prevent FW to block |
| * the driver part by range register, so it must start at the next (48MB) page |
| */ |
| hbm_drv_base_offset = roundup(CPU_FW_IMAGE_SIZE, prop->num_functional_hbms * SZ_8M); |
| |
| /* |
| * The NIC driver section size and the HMMU page tables section in the HBM needs |
| * to be the remaining size in the first dram page after taking into |
| * account the F/W image size |
| */ |
| |
| /* Reserve region in HBM for HMMU page tables */ |
| prop->mmu_pgt_addr = DRAM_PHYS_BASE + hbm_drv_base_offset + |
| ((prop->dram_page_size - hbm_drv_base_offset) - |
| (HMMU_PAGE_TABLES_SIZE + EDMA_PQS_SIZE + EDMA_SCRATCHPAD_SIZE)); |
| |
| /* Set EDMA PQs HBM addresses */ |
| edma_pq_base_addr = prop->mmu_pgt_addr + HMMU_PAGE_TABLES_SIZE; |
| |
| for (i = 0 ; i < GAUDI2_QUEUE_ID_CPU_PQ ; i++) { |
| if (gaudi2_is_edma_queue_id(i)) { |
| prop->hw_queues_props[i].q_dram_bd_address = edma_pq_base_addr + |
| (edma_idx * HL_QUEUE_SIZE_IN_BYTES); |
| edma_idx++; |
| } |
| } |
| |
| return 0; |
| } |
| |
| static int gaudi2_set_fixed_properties(struct hl_device *hdev) |
| { |
| struct asic_fixed_properties *prop = &hdev->asic_prop; |
| struct hw_queue_properties *q_props; |
| u32 num_sync_stream_queues = 0; |
| int i, rc; |
| |
| prop->max_queues = GAUDI2_QUEUE_ID_SIZE; |
| prop->hw_queues_props = kcalloc(prop->max_queues, sizeof(struct hw_queue_properties), |
| GFP_KERNEL); |
| |
| if (!prop->hw_queues_props) |
| return -ENOMEM; |
| |
| q_props = prop->hw_queues_props; |
| |
| for (i = 0 ; i < GAUDI2_QUEUE_ID_CPU_PQ ; i++) { |
| q_props[i].type = QUEUE_TYPE_HW; |
| q_props[i].driver_only = 0; |
| |
| if (i >= GAUDI2_QUEUE_ID_NIC_0_0 && i <= GAUDI2_QUEUE_ID_NIC_23_3) { |
| q_props[i].supports_sync_stream = 0; |
| } else { |
| q_props[i].supports_sync_stream = 1; |
| num_sync_stream_queues++; |
| } |
| |
| q_props[i].cb_alloc_flags = CB_ALLOC_USER; |
| |
| if (gaudi2_is_edma_queue_id(i)) |
| q_props[i].dram_bd = 1; |
| } |
| |
| q_props[GAUDI2_QUEUE_ID_CPU_PQ].type = QUEUE_TYPE_CPU; |
| q_props[GAUDI2_QUEUE_ID_CPU_PQ].driver_only = 1; |
| q_props[GAUDI2_QUEUE_ID_CPU_PQ].cb_alloc_flags = CB_ALLOC_KERNEL; |
| |
| prop->cache_line_size = DEVICE_CACHE_LINE_SIZE; |
| prop->cfg_base_address = CFG_BASE; |
| prop->device_dma_offset_for_host_access = HOST_PHYS_BASE_0; |
| prop->host_base_address = HOST_PHYS_BASE_0; |
| prop->host_end_address = prop->host_base_address + HOST_PHYS_SIZE_0; |
| prop->max_pending_cs = GAUDI2_MAX_PENDING_CS; |
| prop->completion_queues_count = GAUDI2_RESERVED_CQ_NUMBER; |
| prop->user_dec_intr_count = NUMBER_OF_DEC; |
| prop->user_interrupt_count = GAUDI2_IRQ_NUM_USER_LAST - GAUDI2_IRQ_NUM_USER_FIRST + 1; |
| prop->completion_mode = HL_COMPLETION_MODE_CS; |
| prop->sync_stream_first_sob = GAUDI2_RESERVED_SOB_NUMBER; |
| prop->sync_stream_first_mon = GAUDI2_RESERVED_MON_NUMBER; |
| |
| prop->sram_base_address = SRAM_BASE_ADDR; |
| prop->sram_size = SRAM_SIZE; |
| prop->sram_end_address = prop->sram_base_address + prop->sram_size; |
| prop->sram_user_base_address = prop->sram_base_address + SRAM_USER_BASE_OFFSET; |
| |
| prop->hints_range_reservation = true; |
| |
| prop->rotator_enabled_mask = BIT(NUM_OF_ROT) - 1; |
| |
| prop->max_asid = 2; |
| |
| prop->dmmu.pgt_size = HMMU_PAGE_TABLES_SIZE; |
| prop->mmu_pte_size = HL_PTE_SIZE; |
| |
| prop->dmmu.hop_shifts[MMU_HOP0] = DHOP0_SHIFT; |
| prop->dmmu.hop_shifts[MMU_HOP1] = DHOP1_SHIFT; |
| prop->dmmu.hop_shifts[MMU_HOP2] = DHOP2_SHIFT; |
| prop->dmmu.hop_shifts[MMU_HOP3] = DHOP3_SHIFT; |
| prop->dmmu.hop_masks[MMU_HOP0] = DHOP0_MASK; |
| prop->dmmu.hop_masks[MMU_HOP1] = DHOP1_MASK; |
| prop->dmmu.hop_masks[MMU_HOP2] = DHOP2_MASK; |
| prop->dmmu.hop_masks[MMU_HOP3] = DHOP3_MASK; |
| prop->dmmu.page_size = PAGE_SIZE_1GB; |
| prop->dmmu.num_hops = MMU_ARCH_4_HOPS; |
| prop->dmmu.last_mask = LAST_MASK; |
| prop->dmmu.host_resident = 0; |
| prop->dmmu.hop_table_size = HOP_TABLE_SIZE_512_PTE; |
| prop->dmmu.hop0_tables_total_size = HOP_TABLE_SIZE_512_PTE * prop->max_asid; |
| |
| /* As we need to set the pgt address in dram for HMMU init so we cannot |
| * wait to the fw cpucp info to set the dram props as mmu init comes before |
| * hw init |
| */ |
| rc = hdev->asic_funcs->set_dram_properties(hdev); |
| if (rc) |
| goto free_qprops; |
| |
| prop->mmu_pgt_size = PMMU_PAGE_TABLES_SIZE; |
| |
| prop->pmmu.pgt_size = prop->mmu_pgt_size; |
| hdev->pmmu_huge_range = true; |
| prop->pmmu.host_resident = 1; |
| prop->pmmu.num_hops = MMU_ARCH_6_HOPS; |
| prop->pmmu.last_mask = LAST_MASK; |
| prop->pmmu.hop_table_size = HOP_TABLE_SIZE_512_PTE; |
| prop->pmmu.hop0_tables_total_size = HOP_TABLE_SIZE_512_PTE * prop->max_asid; |
| |
| prop->hints_host_reserved_va_range.start_addr = RESERVED_VA_FOR_VIRTUAL_MSIX_DOORBELL_START; |
| prop->hints_host_reserved_va_range.end_addr = RESERVED_VA_RANGE_FOR_ARC_ON_HOST_END; |
| prop->hints_host_hpage_reserved_va_range.start_addr = |
| RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_START; |
| prop->hints_host_hpage_reserved_va_range.end_addr = |
| RESERVED_VA_RANGE_FOR_ARC_ON_HOST_HPAGE_END; |
| |
| if (PAGE_SIZE == SZ_64K) { |
| prop->pmmu.hop_shifts[MMU_HOP0] = HOP0_SHIFT_64K; |
| prop->pmmu.hop_shifts[MMU_HOP1] = HOP1_SHIFT_64K; |
| prop->pmmu.hop_shifts[MMU_HOP2] = HOP2_SHIFT_64K; |
| prop->pmmu.hop_shifts[MMU_HOP3] = HOP3_SHIFT_64K; |
| prop->pmmu.hop_shifts[MMU_HOP4] = HOP4_SHIFT_64K; |
| prop->pmmu.hop_shifts[MMU_HOP5] = HOP5_SHIFT_64K; |
| prop->pmmu.hop_masks[MMU_HOP0] = HOP0_MASK_64K; |
| prop->pmmu.hop_masks[MMU_HOP1] = HOP1_MASK_64K; |
| prop->pmmu.hop_masks[MMU_HOP2] = HOP2_MASK_64K; |
| prop->pmmu.hop_masks[MMU_HOP3] = HOP3_MASK_64K; |
| prop->pmmu.hop_masks[MMU_HOP4] = HOP4_MASK_64K; |
| prop->pmmu.hop_masks[MMU_HOP5] = HOP5_MASK_64K; |
| prop->pmmu.start_addr = VA_HOST_SPACE_PAGE_START; |
| prop->pmmu.end_addr = VA_HOST_SPACE_PAGE_END; |
| prop->pmmu.page_size = PAGE_SIZE_64KB; |
| |
| /* shifts and masks are the same in PMMU and HPMMU */ |
| memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu)); |
| prop->pmmu_huge.page_size = PAGE_SIZE_16MB; |
| prop->pmmu_huge.start_addr = VA_HOST_SPACE_HPAGE_START; |
| prop->pmmu_huge.end_addr = VA_HOST_SPACE_HPAGE_END; |
| } else { |
| prop->pmmu.hop_shifts[MMU_HOP0] = HOP0_SHIFT_4K; |
| prop->pmmu.hop_shifts[MMU_HOP1] = HOP1_SHIFT_4K; |
| prop->pmmu.hop_shifts[MMU_HOP2] = HOP2_SHIFT_4K; |
| prop->pmmu.hop_shifts[MMU_HOP3] = HOP3_SHIFT_4K; |
| prop->pmmu.hop_shifts[MMU_HOP4] = HOP4_SHIFT_4K; |
| prop->pmmu.hop_shifts[MMU_HOP5] = HOP5_SHIFT_4K; |
| prop->pmmu.hop_masks[MMU_HOP0] = HOP0_MASK_4K; |
| prop->pmmu.hop_masks[MMU_HOP1] = HOP1_MASK_4K; |
| prop->pmmu.hop_masks[MMU_HOP2] = HOP2_MASK_4K; |
| prop->pmmu.hop_masks[MMU_HOP3] = HOP3_MASK_4K; |
| prop->pmmu.hop_masks[MMU_HOP4] = HOP4_MASK_4K; |
| prop->pmmu.hop_masks[MMU_HOP5] = HOP5_MASK_4K; |
| prop->pmmu.start_addr = VA_HOST_SPACE_PAGE_START; |
| prop->pmmu.end_addr = VA_HOST_SPACE_PAGE_END; |
| prop->pmmu.page_size = PAGE_SIZE_4KB; |
| |
| /* shifts and masks are the same in PMMU and HPMMU */ |
| memcpy(&prop->pmmu_huge, &prop->pmmu, sizeof(prop->pmmu)); |
| prop->pmmu_huge.page_size = PAGE_SIZE_2MB; |
| prop->pmmu_huge.start_addr = VA_HOST_SPACE_HPAGE_START; |
| prop->pmmu_huge.end_addr = VA_HOST_SPACE_HPAGE_END; |
| } |
| |
| prop->max_num_of_engines = GAUDI2_ENGINE_ID_SIZE; |
| prop->num_engine_cores = CPU_ID_MAX; |
| prop->cfg_size = CFG_SIZE; |
| prop->num_of_events = GAUDI2_EVENT_SIZE; |
| |
| prop->supports_engine_modes = true; |
| |
| prop->dc_power_default = DC_POWER_DEFAULT; |
| |
| prop->cb_pool_cb_cnt = GAUDI2_CB_POOL_CB_CNT; |
| prop->cb_pool_cb_size = GAUDI2_CB_POOL_CB_SIZE; |
| prop->pcie_dbi_base_address = CFG_BASE + mmPCIE_DBI_BASE; |
| prop->pcie_aux_dbi_reg_addr = CFG_BASE + mmPCIE_AUX_DBI; |
| |
| strscpy_pad(prop->cpucp_info.card_name, GAUDI2_DEFAULT_CARD_NAME, CARD_NAME_MAX_LEN); |
| |
| prop->mme_master_slave_mode = 1; |
| |
| prop->first_available_user_sob[0] = GAUDI2_RESERVED_SOB_NUMBER + |
| (num_sync_stream_queues * HL_RSVD_SOBS); |
| |
| prop->first_available_user_mon[0] = GAUDI2_RESERVED_MON_NUMBER + |
| (num_sync_stream_queues * HL_RSVD_MONS); |
| |
| prop->first_available_user_interrupt = GAUDI2_IRQ_NUM_USER_FIRST; |
| prop->tpc_interrupt_id = GAUDI2_IRQ_NUM_TPC_ASSERT; |
| prop->eq_interrupt_id = GAUDI2_IRQ_NUM_EVENT_QUEUE; |
| |
| prop->first_available_cq[0] = GAUDI2_RESERVED_CQ_NUMBER; |
| |
| prop->fw_cpu_boot_dev_sts0_valid = false; |
| prop->fw_cpu_boot_dev_sts1_valid = false; |
| prop->hard_reset_done_by_fw = false; |
| prop->gic_interrupts_enable = true; |
| |
| prop->server_type = HL_SERVER_TYPE_UNKNOWN; |
| |
| prop->max_dec = NUMBER_OF_DEC; |
| |
| prop->clk_pll_index = HL_GAUDI2_MME_PLL; |
| |
| prop->dma_mask = 64; |
| |
| prop->hbw_flush_reg = mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0; |
| |
| prop->supports_advanced_cpucp_rc = true; |
| |
| return 0; |
| |
| free_qprops: |
| kfree(prop->hw_queues_props); |
| return rc; |
| } |
| |
| static int gaudi2_pci_bars_map(struct hl_device *hdev) |
| { |
| static const char * const name[] = {"CFG_SRAM", "MSIX", "DRAM"}; |
| bool is_wc[3] = {false, false, true}; |
| int rc; |
| |
| rc = hl_pci_bars_map(hdev, name, is_wc); |
| if (rc) |
| return rc; |
| |
| hdev->rmmio = hdev->pcie_bar[SRAM_CFG_BAR_ID] + (CFG_BASE - STM_FLASH_BASE_ADDR); |
| |
| return 0; |
| } |
| |
| static u64 gaudi2_set_hbm_bar_base(struct hl_device *hdev, u64 addr) |
| { |
| struct gaudi2_device *gaudi2 = hdev->asic_specific; |
| struct hl_inbound_pci_region pci_region; |
| u64 old_addr = addr; |
| int rc; |
| |
| if ((gaudi2) && (gaudi2->dram_bar_cur_addr == addr)) |
| return old_addr; |
| |
| if (hdev->asic_prop.iatu_done_by_fw) |
| return U64_MAX; |
| |
| /* Inbound Region 2 - Bar 4 - Point to DRAM */ |
| pci_region.mode = PCI_BAR_MATCH_MODE; |
| pci_region.bar = DRAM_BAR_ID; |
| pci_region.addr |