// SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Device Tree Source for AM64 SoC Family MCU Domain peripherals
 *
 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
 */

&cbass_mcu {
	/*
	 * The MCU domain timer interrupts are routed only to the ESM module,
	 * and not currently available for Linux. The MCU domain timers are
	 * of limited use without interrupts, and likely reserved by the ESM.
	 */
	mcu_timer0: timer@4800000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x4800000 0x00 0x400>;
		clocks = <&k3_clks 35 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	mcu_timer1: timer@4810000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x4810000 0x00 0x400>;
		clocks = <&k3_clks 48 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	mcu_timer2: timer@4820000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x4820000 0x00 0x400>;
		clocks = <&k3_clks 49 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 49 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	mcu_timer3: timer@4830000 {
		compatible = "ti,am654-timer";
		reg = <0x00 0x4830000 0x00 0x400>;
		clocks = <&k3_clks 50 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 50 TI_SCI_PD_EXCLUSIVE>;
		ti,timer-pwm;
		status = "reserved";
	};

	mcu_uart0: serial@4a00000 {
		compatible = "ti,am64-uart", "ti,am654-uart";
		reg = <0x00 0x04a00000 0x00 0x100>;
		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 149 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	mcu_uart1: serial@4a10000 {
		compatible = "ti,am64-uart", "ti,am654-uart";
		reg = <0x00 0x04a10000 0x00 0x100>;
		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 160 0>;
		clock-names = "fclk";
		status = "disabled";
	};

	mcu_i2c0: i2c@4900000 {
		compatible = "ti,am64-i2c", "ti,omap4-i2c";
		reg = <0x00 0x04900000 0x00 0x100>;
		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 106 2>;
		clock-names = "fck";
		status = "disabled";
	};

	mcu_i2c1: i2c@4910000 {
		compatible = "ti,am64-i2c", "ti,omap4-i2c";
		reg = <0x00 0x04910000 0x00 0x100>;
		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 107 2>;
		clock-names = "fck";
		status = "disabled";
	};

	mcu_spi0: spi@4b00000 {
		compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
		reg = <0x00 0x04b00000 0x00 0x400>;
		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 147 0>;
		status = "disabled";
	};

	mcu_spi1: spi@4b10000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x04b10000 0x00 0x400>;
		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 148 0>;
		status = "disabled";
	};

	mcu_gpio_intr: interrupt-controller@4210000 {
		compatible = "ti,sci-intr";
		reg = <0x00 0x04210000 0x00 0x200>;
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <5>;
		ti,interrupt-ranges = <0 104 4>;
	};

	mcu_gpio0: gpio@4201000 {
		compatible = "ti,am64-gpio", "ti,keystone-gpio";
		reg = <0x0 0x4201000 0x0 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&mcu_gpio_intr>;
		interrupts = <30>, <31>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <23>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 79 0>;
		clock-names = "gpio";
	};

	mcu_pmx0: pinctrl@4084000 {
		bootph-all;
		compatible = "pinctrl-single";
		reg = <0x00 0x4084000 0x00 0x84>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	mcu_esm: esm@4100000 {
		bootph-pre-ram;
		compatible = "ti,j721e-esm";
		reg = <0x00 0x4100000 0x00 0x1000>;
		/* Interrupt sources: esm0_cfg, esm0_hi, esm0_low, mrti0 */
		ti,esm-pins = <0>, <1>, <2>, <85>;
	};
};