tree 4e25f8e1b76328c7d7794cc277aebdbd6f445535
parent 7e2570031a1a47ff993eb2db68718dad6a2f93ec
parent 60b8f0ddf1a927ef02141a6610fd52575134f821
parent d3236214e7dead87e7aefd32259aaf0bf41cf050
parent da392a5ab4111d336e2b2b724499ad05ee9845a0
parent a9ca321716c801ae4e731b3a016c24633374b59b
parent df446f7e6ec0ed474dab2e6f19e4618116907f29
author Stephen Boyd <sboyd@kernel.org> 1552069641 -0800
committer Stephen Boyd <sboyd@kernel.org> 1552069641 -0800

Merge branches 'clk-optional', 'clk-devm-clkdev-register', 'clk-allwinner', 'clk-meson' and 'clk-renesas' into clk-next

 - Add a {devm_}clk_get_optional() API
 - Add devm_clk_hw_register_clkdev() API to manage clkdev lookups

* clk-optional:
  clk: Add (devm_)clk_get_optional() functions
  clk: Add comment about __of_clk_get_by_name() error values

* clk-devm-clkdev-register:
  clk: clk-st: avoid clkdev lookup leak at remove
  clk: clk-max77686: Clean clkdev lookup leak and use devm
  clkdev: add managed clkdev lookup registration

* clk-allwinner:
  clk: sunxi-ng: sun8i-a23: Enable PLL-MIPI LDOs when ungating it

* clk-meson: (22 commits)
  clk: meson: meson8b: fix the naming of the APB clocks
  dt-bindings: clock: meson8b: add APB clock definition
  clk: meson: Add G12A AO Clock + Reset Controller
  dt-bindings: clk: add G12A AO Clock and Reset Bindings
  clk: meson: factorise meson64 peripheral clock controller drivers
  clk: meson: g12a: add peripheral clock controller
  dt-bindings: clk: meson: add g12a periph clock controller bindings
  clk: meson: pll: update driver for the g12a
  clk: meson: rework and clean drivers dependencies
  clk: meson: axg-audio does not require syscon
  clk: meson: use CONFIG_ARCH_MESON to enter meson clk directory
  clk: export some clk_hw function symbols for module drivers
  clk: meson: ao-clkc: claim clock controller input clocks from DT
  clk: meson: axg: claim clock controller input clock from DT
  clk: meson: gxbb: claim clock controller input clock from DT
  clk: meson: meson8b: add the GPU clock tree
  clk: meson: meson8b: use a separate clock table for Meson8
  clk: meson: axg-ao: add 32k generation subtree
  clk: meson: gxbb-ao: replace cec-32k with the dual divider
  clk: meson: add dual divider clock driver
  ...

* clk-renesas:
  clk: renesas: r8a774a1: Fix LAST_DT_CORE_CLK
  clk: renesas: r8a774c0: Fix LAST_DT_CORE_CLK
  clk: renesas: r8a774c0: Add TMU clock
  clk: renesas: r8a77980: Add RPC clocks
  clk: renesas: rcar-gen3: Add RPC clocks
  clk: renesas: rcar-gen3: Add spinlock
  clk: renesas: rcar-gen3: Factor out cpg_reg_modify()
  clk: renesas: r8a774c0: Correct parent clock of DU
  clk: renesas: r8a774a1: Add missing CANFD clock
  clk: renesas: r8a774c0: Add missing CANFD clock