tree 06f9ea2dd308fa882cff4f9fc5d951aace3b1eb8
parent 684c1664e0de63398aceb748343541b48d398710
author Christophe Leroy <christophe.leroy@csgroup.eu> 1589867356 +0000
committer Michael Ellerman <mpe@ellerman.id.au> 1590495742 +1000

powerpc/8xx: Drop special handling of Linear and IMMR mappings in I/D TLB handlers

Up to now, linear and IMMR mappings are managed via huge TLB entries
through specific code directly in TLB miss handlers. This implies
some patching of the TLB miss handlers at startup, and a lot of
dedicated code.

Remove all this specific dedicated code.

For now we are back to normal handling via standard 4k pages. In the
next patches, linear memory mapping and IMMR mapping will be managed
through huge pages.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/221b7e3ead80a5969629938c023f8cfe45fdd2fb.1589866984.git.christophe.leroy@csgroup.eu