#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "sigma,tango4-smp";

		cpu0: cpu@0 {
			compatible = "arm,cortex-a9";
			next-level-cache = <&l2cc>;
			device_type = "cpu";
			reg = <0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a9";
			next-level-cache = <&l2cc>;
			device_type = "cpu";
			reg = <1>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupt-affinity = <&cpu0>, <&cpu1>;
		interrupts =
			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	};
};