// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2023 BayLibre, SAS.
 * Author: Jerome Brunet <jbrunet@baylibre.com>
 */

/dts-v1/;

#include <dt-bindings/clock/g12a-clkc.h>
#include "meson-sm1.dtsi"
#include "meson-libretech-cottonwood.dtsi"

/ {
	compatible = "libretech,aml-s905d3-cc", "amlogic,sm1";
	model = "Libre Computer AML-S905D3-CC Solitude";

	sound {
		model = "LC-SOLITUDE";
		audio-routing = "TDMOUT_A IN 0", "FRDDR_A OUT 0",
				"TDMOUT_A IN 1", "FRDDR_B OUT 0",
				"TDMOUT_A IN 2", "FRDDR_C OUT 0",
				"TDM_A Playback", "TDMOUT_A OUT",
				"TDMOUT_B IN 0", "FRDDR_A OUT 1",
				"TDMOUT_B IN 1", "FRDDR_B OUT 1",
				"TDMOUT_B IN 2", "FRDDR_C OUT 1",
				"TDM_B Playback", "TDMOUT_B OUT",
				"TDMOUT_C IN 0", "FRDDR_A OUT 2",
				"TDMOUT_C IN 1", "FRDDR_B OUT 2",
				"TDMOUT_C IN 2", "FRDDR_C OUT 2",
				"TDM_C Playback", "TDMOUT_C OUT",
				"TDMIN_A IN 0", "TDM_A Capture",
				"TDMIN_B IN 0", "TDM_A Capture",
				"TDMIN_C IN 0", "TDM_A Capture",
				"TDMIN_A IN 13", "TDM_A Loopback",
				"TDMIN_B IN 13", "TDM_A Loopback",
				"TDMIN_C IN 13", "TDM_A Loopback",
				"TDMIN_A IN 1", "TDM_B Capture",
				"TDMIN_B IN 1", "TDM_B Capture",
				"TDMIN_C IN 1", "TDM_B Capture",
				"TDMIN_A IN 14", "TDM_B Loopback",
				"TDMIN_B IN 14", "TDM_B Loopback",
				"TDMIN_C IN 14", "TDM_B Loopback",
				"TDMIN_A IN 2", "TDM_C Capture",
				"TDMIN_B IN 2", "TDM_C Capture",
				"TDMIN_C IN 2", "TDM_C Capture",
				"TDMIN_A IN 15", "TDM_C Loopback",
				"TDMIN_B IN 15", "TDM_C Loopback",
				"TDMIN_C IN 15", "TDM_C Loopback",
				"TODDR_A IN 0", "TDMIN_A OUT",
				"TODDR_B IN 0", "TDMIN_A OUT",
				"TODDR_C IN 0", "TDMIN_A OUT",
				"TODDR_A IN 1", "TDMIN_B OUT",
				"TODDR_B IN 1", "TDMIN_B OUT",
				"TODDR_C IN 1", "TDMIN_B OUT",
				"TODDR_A IN 2", "TDMIN_C OUT",
				"TODDR_B IN 2", "TDMIN_C OUT",
				"TODDR_C IN 2", "TDMIN_C OUT",
				"Lineout", "ACODEC LOLP",
				"Lineout", "ACODEC LORP";
	};
};

&cpu0 {
	cpu-supply = <&vddcpu_b>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU_CLK>;
	clock-latency = <50000>;
};

&cpu1 {
	cpu-supply = <&vddcpu_b>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU1_CLK>;
	clock-latency = <50000>;
};

&cpu2 {
	cpu-supply = <&vddcpu_b>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU2_CLK>;
	clock-latency = <50000>;
};

&cpu3 {
	cpu-supply = <&vddcpu_b>;
	operating-points-v2 = <&cpu_opp_table>;
	clocks = <&clkc CLKID_CPU3_CLK>;
	clock-latency = <50000>;
};